SuperSpeed USB 3.0 is 10x the speed and accordingly more than 10x the complexity. Consequently, many companies will take a course to acquire third-party IP rather than develop it in-house. This changes the verification challenge from one of compliance to one of integration, which doesn’t necessarily reduce the verification effort but does change the focus. This article covers some of the fundamental steps needed to successfully verify your USB 3.0 design.

SuperSpeed USB—also known as USB 3.0—is a new, complex protocol that delivers a 10x performance increase over Hi-Speed USB 2.0, massively reducing transfer times for digital consumer devices. What’s more is that it is backwards compatible with Hi-Speed USB, meaning that your new USB 3.0 flash drive, media player or digital camera will work with your old desktop PC (using a USB 2.0 connector) and your new laptop (using a USB 3.0 connector).  However, the protocol complexity of USB 3.0 is at least 10x that of USB 2.0 because of new features like streaming, bursting and deferred packet handling.  This high level of complexity means that designers who are incorporating USB 3.0 cores into their designs need to use an advanced, disciplined approach to verification to ensure high-yielding chips and low return-rate end-products.

In order to verify the integration of a USB 3.0 digital controller into a larger design using a combination of directed and constrained random testing, there are a number of verification techniques to explore. The task of adding SuperSpeed USB 3.0 to an existing 2.0 design and ensuring backwards and forwards compatibility is, by no means, trivial. SuperSpeed USB 3.0 requires a new analog physical layer (PHY) to handle new, faster dual-simplex signaling, spread-spectrum and asynchronous clocking. It has independent transmit and receive lines to allow simultaneous transmission and reception at 5 Gbps. USB 3.0 also requires a new controller to process, packetize and decode the new protocol and incorporate new features like streams and bursting that are needed to achieve the higher USB 3.0 throughputs; and of course the USB 3.0 digital controller must be able to handle both USB 3.0 and 2.0 traffic. Finally, new software drivers are required to enable both forward and backwards compatibility between USB 3.0 and USB 2.0 products to make the user experience seamless.

Given this level of additional complexity, it is reasonable to expect that most companies will opt to acquire the IP for USB 3.0 from companies with a proven history in delivering high-quality USB IP products. The verification challenge for most people will therefore be to focus verification on the integration of a USB 3.0 core into a larger design rather than running tests targeted at their own USB 3.0 design compliance, which should be the major focus for the IP vendor.

With the knowledge that extensive verification of the digital core should have already been completed by the third-party IP vendor, the focus of integration testing should be to verify that the digital core has been properly integrated into the system, can communicate with the processor/memory blocks and plays nicely with the other blocks that it competes with for bus bandwidth. The challenge should not be underestimated or seen as a subset of compliance, however. It simply has a different focus, which is to ensure that the digital cores and PHYs in the design have been correctly integrated and are meeting their expected functional and performance goals.

Most of the core’s interaction with the design will typically be CPU access to the core’s registers and the core’s access of the system memory through the built-in DMA master interface. This handles the transfers into system memory and perhaps to other interfaces in the design at the same time that the CPU is performing other tasks on the bus.

Using a USB 3.0 device core as an example, we will look into the integration tests, which can encompass everything from simple connectivity tests to some advanced performance analysis. On the USB side of the digital core is USB Verification IP (VIP) that can handle all speeds specified by USB 3.0. On the application side are blocks of RTL communicating through the system buses.  Verification IP may be used for blocks that are not yet completed, or for simulation purposes that are faster and simpler to run with VIP or C models than with the RTL.  A mixture of these can be used.

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The first step in verifying the basic connectivity is best accomplished with a few reads and writes to and from the DMA.  The most basic test is to verify reads and writes from the system bus to the USB 3.0 device registers and FIFOs. Once this basic connectivity has been established, the next step is to initialize the core in the same way that the driver software would enumerate the core, and run data from the USB port through to the DMA and beyond.  After running through the link initialization process, which includes training sets and verifying buffer availability, the device is ready to receive payload data. The payload data  is passed through the core, up to the DMA and onto system memory where it is verified against the data that was sent by the verification IP.  A system bus monitor can provide bus utilization information. It is not relevant at this time to create other bus activity on the internal buses since the requirement is purely one of connectivity.

This example uses a DesignWare digital core with integrated USB 2.0 and 3.0 devices, so at this time it is not really necessary to try different speeds since they are essentially equivalent from an integration perspective. At some point, however, most engineers will want to verify that the digital core initializes at SuperSpeed USB 3.0 then switches down to Hi-Speed to test for the case that the USB 3.0 Host at the other end does not support SuperSpeed USB. This should be easily achievable by the VIP.

Now that connectivity and interaction with the DMA is verified, the next step is to run through other scenarios relevant to correct system function. These tests typically include power management tests like power up and power down initiated by the SoC, suspend and resume, and disconnect and connect. These can also be accomplished easily from the VIP side by using the service channel which, is built into the VIP.

Once these tests have been verified, the interesting task of investigating system performance can begin, including the testing of latencies between transfers and memory, and between the USB port and the appearance of the data on other interfaces in the design (e.g., PCI Express®). There are two aspects to this: the buffer size that was configured in the core and the rate at which data is being transferred compared to the system bus activity. Different transfer speeds can easily be set in the VIP, and then randomization can be used to stress the design with a high volume of traffic using the four different transfer types:   bulk, isochronous, interrupt and control.  Each transfer type has its own different bandwidth and service interval characteristics.  In parallel, on the application side, the other blocks in the design should simulate the activity and background traffic that is competing for the bus. A performance monitor, included with the DesignWare digital core testbench, looks at the overall bus activity and helps verification engineers to identify potential issues.

The verification can be done independently of a PHY in the design using the PIPE interface between the VIP and core.  A PHY can be connected to the digital core at the PIPE interface and to the VIP’s RX/TX interface, as shown in the diagram (above).  The verification IP should provide a layered architecture, which makes it easy for verification engineers to interact at the transfer level to create different transfer types and packet types at the link layer to control power management and LTSSM states, as well as at the PHY layer. The VIP should be capable of injecting errors in order to test the error conditions like control aborts, multiple CRC errors, etc. that propagate up to the application layer.

The DesignWare Verification IP for USB 3.0 complements the DesignWare digital core by providing all of the capabilities needed for integration testing plus any additional testing required, achieving coverage goals. A separate integration test suite will be targeted at helping engineers verify that USB 3.0 digital cores are integrated into their design and functioning as needed for the expected system behavior and performance. The DesignWare USB 3.0 digital core also includes a Verilog testbench, which helps verification engineers with the first steps in verifying the integration of the design.