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Published on November 06th, 2009
In December, Juniper Networks will make available products in its new MX 3D family of line cards and routers, devices the company claims can process up to four times more traffic - up to 2.6 Tbits/s - than competitive products with half the power per gigabit. According to Juniper, the line’s flagship MX960 3D, for instance, is rated at about 37 W per 10 GE, compared with 75 W and 90 W per 10 GE for competitive products. The MX960 3D is powerful and fast, enabling subscribers to download 8.5 million iTunes songs in one-tenth of a second or access 10 years of Hubble data in one minute.
The driving force behind this power is Juniper’s new Trio chipset, which the company unveiled recently during a launch event - at the New York Stock Exchange - that coincided with the 40th anniversary of the first ARPANET link between UCLA and Stanford researchers. During the event, Juniper’s vice chairman, CTO, and founder Pradeep Sindhu referred to Trio’s development as "the single-most significant advance in networking history since 1998," when Juniper released its first networking IPP4 and MPLS chipsets. Trio is the company’s fourth generation of purpose-built silicon, and the first in Juniper’s new Junos One processor family.
Trio is built on the company’s new proprietary silicon architecture - dubbed "network instruction set" - which leverages custom network instructions designed in the silicon and works closely with software to enable programmability of network resources. The network instruction set basically combines the performance benefits of ASICS and the flexibility of NPUs, and eliminates the need to suffer tradeoffs between the two.
"Pretty soon, most of the traffic over the internet will be flowing over these chips," Sindhu said. "It’s the chip that runs the new network."
That new network was the main focus of the Juniper event, a network that will enable what the company has dubbed 3D scaling, where networks can scale dynamically for bandwidth, subscribers, and services at the same time without compromise. "3D scaling is one of those rare technology breakthroughs that can change business models," said Kim Perdikou, executive VP and general manager of Juniper’s Infrastructure Products Group. Trio is the backbone of this effort.
Built on 65-nm technology, the Trio chipset comprises - somewhat ironically considering the name - four chips with 1.5 billion transistors. The device is capable of 320 simultaneous processes, yields a total router throughput as high as 2.6 Tbits/s, and supports up to 2.3 million subscribers per rack.
The chipset is made up of a queuing engine, an interface engine, a lookup engine that is the brains of the device, and a memory engine which Sindhu refers to as the "braun" and "muscle" of the chipset. "This is the most advanced memory system designed - on the planet." Trio features an impressive pin count of 2,450, with a little more than 10% of those supporting Ultra-High Speed operation.
The innovations in the Trio chipset are represented by more than 30 patents pending in silicon architecture, packet processing, quality of service, and energy efficiency. Of course, development the device did not happen overnight.
The company invested more than $80 million over the past five years in the design of trio, an effort that expended about 1.6 million CPU hours. Sindhu and Juniper believe, of course, it was utterly worth the effort, both for the company, and, more importantly, its customers, saying it will yield "a fundamental advance in performance, flexibility, and power efficiency to meet the Internet’s massive three-dimensional scaling needs."
"This will dramatically change the economics for our customers, while helping them [to] create new and better experiences for their customers. This is the platform for the next decade."
Juniper, of course, will not be selling its new chipset to designers. Leveraging the technology means using the new lines of modular line cards, metro aggregation routers, and new applications that will be released in the coming months. The first of these will be the company’s MX 3D devices, which were also announced during the event.
Said to be the industry’s first 120-Gbit/s device of its type, the MX 3D Aggregation line card is claimed to also offer the highest 10-GbE density for aggregation, video distribution, data center, and edge routing. The MX 3D 100-GbE line card is offered as the industry’s only edge-routing device with line-rate 100-GbE performance for edge uplink, inter-data center, and high-bandwidth aggregation.
The MX80 Series 3D 3.5-in. routers claim to be eight times faster than competitors to suit delivery of Carrier Ethernet services for multi-tenant buildings, as well as mobile aggregation, video and enterprise edge deployments. Two third-party applications being developed on the Junos operating system and Juniper’s MX Series are an Active Broadband Networks application for monitoring cable bandwidth and usage, and an Ankeena Networks application for video streaming and caching.
Ralph Raiola is a professional writer and editor with more than 13 years experience in traditional and new media. As an editor for more than nine years at Electronic Products Magazine, he covered beats as varied as Passive Components, Interconnects, Thermal Management, Motors, and Switches and Relays. Based in Hauppauge, NY, Ralph is currently a freelance editor and writer for several publications and businesses worldwide. Find out more at http://ralphraiola.com.