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C'mon Rock 'n' Chip Fans, Join the Chip Synthesis Revolution
Yeah, this is a revolution – right here, right now. Buck up and get your wings. Rock your shop. Change your world. Come on feel the noise with the molten-metal power shower of the Chip Synthesis Revolution.
Remember, rock 'n' chip fans, when you thought logic synthesis was the real deal, where it was at, what really mattered? Well, forget about it. A revolution called Chip Synthesis is about to trash everything you know, crank the volume past 11, melt your mind with extreme heat and blow up your entire world.
- We'll fight, yeah,
You'll see, yeah,
We're not gonna take it,
No, we ain't gonna take it,
No more logic synthesis anymore.
No way!
You don't believe me? Well, a flaming fireball dropped from great height and crashed the electronic design automation (EDA) party. Prepare to get rocked because a seasoned software team has been at it for a long time and is bringing a world of silicon hurt to the table, especially when we're talking integrated circuit (IC) design. You are about to be dazzled by the shock-and-awe wonder of the Chip Synthesis Revolution.
- Welcome to the IC jungle,
It gets worse here everyday,
Ya learn ta live with long runtimes
But in this jungle, we innovate!
If you got a hunger for what we do,
You'll take it eventually.
This dazzling new innovation in design creation takes the entire chip design all the way down, from register transfer level (RTL) code to placed gates , if you get my drift – in a single pass. Physical RTL synthesis or Chip Synthesis can handle designs of tens of millions of gates with an off‐the‐shelf PC in a few hours.
Sanjiv (center) standing alongside ... well, you guess
So you want the upshot? Of course you do. Results are as good as or better than results that take days to achieve from the well‐known and boringly traditional mainstream synthesis tools. Final place and route is done with any standard commercial tool and correlates with the predicted performance. What do you say to that, rock 'n' chip fans? Cool, eh?
- Come on feel the noise.
With 60 times runtime, over 100 mil gates,
We'll get wild, wild, wild,
Wild, wild, wild – make some profit, too!
Let's look under the hood. Until now, all synthesis software has been built the same way: turn the RTL code into gates and then optimize those gates to meet the constraints. It's as if C language compilers all worked by turning the C code into machine instructions, and then optimized machine instructions. With enough runtime and clever optimization techniques, working at the machine instruction level might find a higher‐level optimization.
- Another design hits the floor,
Another design hits the floor,
And another design done, and another design done,
With a better floor plan, plus easy adoption.
Hey, we're gonna help you, too,
Another design hits the floor.
Isn't it better to do higher-level optimizations at the higher level in the first place? Of course it is! Modern C compilers are built this way, with global optimizers that look at a high‐level representation of the program, and a straightforward peephole optimizer cleaning up final details at the machine instruction level at the end. Ah! Now you're getting Chip Synthesis.
- Someday he's gonna make it to the top
And be a Chip Synthesis hero, stars in his eyes,
He's a Chip Synthesis hero.
He took one design, cut down the time,
Chip Synthesis hero, he'll come alive tonight.
Yeah, this is a revolution – right here, right now. Buck up and get your wings. Rock your shop. Change your world. Come on feel the noise with the molten-metal power shower of the Chip Synthesis Revolution.
Don't waste another nanosecond. There's a new game in town. Rock on and join the Chip Synthesis Revolution …
- 'Cause the walls start shaking,
The design specs are quaking,
My mind was aching
With a new design platform, and
It shook me all night long.
Yeah, it shook me in real time, in real time.
Marketing Whiz Sanjiv Kaul is executive chairman of Oasys Design Systems. Kaul has a strong track record of growing several of the key businesses in EDA over his 25 year career. At Synopsys, as senior vice president/general manager of the IC Implementation technology, he was responsible for leading the successful expansion of Synopsys' RTL synthesis franchise to leadership in RTL to GDSII. Since leaving Synopsys in 2004, Kaul has been involved with several startups in a variety of industries as an investor, advisor and board member. He has a bachelor of science degree from the University of Delhi and a bachelor of science degree in electrical engineering from the University of Maryland.
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