Published on November 12th, 2009
For over 10 years, design engineers have used the same static timing analysis (STA) approach for sign-off validation. But, as process nodes shrink, gate counts increase and reducing power consumption becomes a key requirement, design teams must reevaluate every aspect of their design methodology from resource planning, design architecture and final sign-off solutions. This is especially true at the 28-nanometer node where designs are expected to exceed 100 million gates, have 15 or more process, voltage and temperature (PVT) corners, supply voltages under 1V and shorter design cycles.
Since its introduction, some minor advances in STA have been made such as the use of composite current models (CCS) models and distributed multi-mode/multi-corner (MM/MC) and location-based on-chip variation (OCV) analysis. Still, even on less complex, higher geometry designs, current STA tools are not meeting designers’ need for higher capacity, greater accuracy and faster turnaround time.
To workaround current STA tool’s limited capacity, designers partition their designs and black-box some portions during analysis, which may compromise accuracy. They also use hierarchical timing models for internal and interface timing paths. These models may not sufficiently capture the interface timing under MM/MC conditions.
At advanced technology nodes it becomes increasingly complicated to capture variations and so the number of PVT corners and amount of analysis increases significantly. Designers build in timing margins through OCV techniques, but this subjective approach is often pessimistic and adversely affects performance and area. To address yield problems, Statistical STA (SSTA) is sometimes added to the flow. Recently, Advanced OCV was introduced in an attempt to reduce the pessimism induced by traditional OCV, but it remains to be seen whether it can truly capture the actual variations at 28 nm and below.
Dealing with variation is particularly challenging in low-voltage designs below 65 nm. Standard delay models will not sufficiently address process variation for designs with supply voltages below 1V. These designs exhibit strong delay nonlinearity with respect to PVT parameter variations. At 65 nm and above additional PVT corners and larger OCV margins can work, but require longer runtimes and a significant investment in additional memory and hardware.
Multiple PVT corners complicate the engineering change order (ECO) process, as well. Traditional place-and-route tools don’t support multi-corner analysis during optimization which may lead to more hold fixes. Traditional timing analysis solutions can’t comprehend the parasitics for the wires that are modified in the ECO. This information is not available until the wires have been incrementally or fully rerouted and re-extracted. Designers often find themselves in a timing closure ping-pong game where an ECO that fixes the original timing violation creates another.
It’s clear that at 28 nm the traditional STA approach of increasing the amount of analysis, number of software licenses and computing resources is no longer viable. Designers need an accurate solution that can time designs with 100 million gate, 15 or more PVT corners and 1V power supply. The solution should support concurrent MM/MC and SSTA. It should integrate timing analysis and capacitance extraction to shorten the ECO cycle. “Bigger and more” won’t work anymore. It’s time for “better,” “smarter,” faster” timing analysis flows.
Robert (Bob) P. Smith rejoined in early 2009 Magma Design Automation as vice president of Product Marketing within the Design Implementation Business Unit after a seven-year absence.
Bob's experience as an executive within the EDA industry dates back to 1987. Most recently, he was chief executive officer (CEO) and chairman of Stratosphere Solutions Inc., and was formerly president and chief executive officer of InTime Software Inc. Bob holds a Master of Science degree in electrical engineering from Stanford University and Bachelor of Science degree in electrical engineering from the University of California at Davis.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446