Published on April 14th, 2006

The Death of the Structured ASIC

My list of the worst semiconductor products would include the Structured ASIC, a device that is not fictitious and is not a joke, but deserves to be one.

Most of us can probably name the best products in the history of semiconductors. The transistor, the integrated circuit, the microprocessor, dynamic RAM, static RAM, the EPROM, the ASIC, and the FPGA would all be on the list. How about the worst products? I might include the write-only memory, a fictitious joke product from my days at Signetics (does anyone remember Signetics?) that consisted of a data sheet for a device that allowed you to dispose of unneeded bits in your system.

My list would also include the Structured ASIC, a device that unfortunately is not fictitious and is not a joke, but deserves to be one. Just a few weeks ago as I pen these words, LSI Logic finally put the first nail in the coffin of this strange creature by announcing that it was dropping support for its RapidChip, one of the first structured ASICs, due to lackluster sales. Let’s hope that other vendors do the same and put this thing out of its misery.

To see why the structured ASIC makes no sense, we need to understand the history – and rivalry – of ASICs and FPGAs.

A Brief History of ASICs and FPGAs
First there was the Application Specific Integrated Circuit or ASIC, pioneered by LSI Logic in the early eighties. The idea was that many companies could get tremendous cost savings by condensing their board logic into a single chip. But most companies didn’t have the money to build a chip fab. And their engineers had little, if any, knowledge of chip layout or semiconductor processing. So semiconductor vendors created development tools and chip architectures that allowed logic to be easily mapped to the chip and characterized with respect to timing and power consumption. They created libraries of logic gates that engineers could use without needing knowledge of the physical properties of the underlying semiconductor structures.

In the early days, there were a few ASIC chip architectures offered by different vendors, but they all quickly converged to two basic architectures, gate arrays and standard cells, as shown in Figure 1.

Figure 1

Figure 1: Application Specific Integrated Circuit (ASIC) architectures

Gate Array ASICs
Gate arrays consisted of regular arrays of unconnected transistors. The chips were complete except for metal layers needed to connect the transistors. The gate array vendor would mass-produce these chips. Software provided by the gate array vendor, called a place-and-route tool, would map the logic gates of the customer’s design – NANDs, NORs, flip-flops, and so forth – to specific transistors on the chip and determine a good way to put metal traces on the chip to connect the transistors so as to complete the design. Because all customers used the same basic platform, the costs associated with creating these base wafers were shared among all the customers. Thus, the initial NRE (non recurring expense) for a gate array was fairly cheap, though it could still be in the thousands or tens of thousands of dollars.

Gate array vendors offered families of gate arrays with a fixed number of transistors. A vendor might offer a 5,000 transistor chip and a 10,000 transistor chip. If your design required 5,001 transistors you were forced to put the design into the 10,000 transistor chip. Utilization of the transistors in a gate array was thus inefficient. Since it costs a fixed amount of money to process a single wafer, the more chip die that fit on that wafer – the cheaper the cost per chip. Conversely, an underutilized gate array meant that the customer paid for all transistors on the chip, even the unused ones. Thus the cost per piece for a gate array was relatively high.

Standard Cell ASICs
The other ASIC architecture was the standard cell, which started as a blank die. The standard cell vendor created a library of logic gates and higher-level logic functions called cells. The customer created a design from this library. The standard cell vendor provided place-and-route software that placed each cell onto the die and wired them all together to create the customer’s design. Because only cells that the design specifically required were placed on the chip, the chips were smaller and thus cost less per piece than a gate array. The tradeoff was that the initial costs were not shared by other customers because each customer’s standard cell chip was completely unique. Thus the standard cell chip had a large NRE.

The cost structure was such that gate arrays were used by companies requiring fewer volumes of chips while standard cells were used by companies requiring higher volumes of chips.

Around the mid-eighties, Xilinx pioneered the Field Programmable Gate Array (FPGA), so-named because its architecture resembled the gate array, but it could be programmed by the customer to perform a specific function. The similarity to the gate array can be seen in Figure 2. With an FPGA, the array consisted not of transistors but of logic blocks that contained memories used to implement logic, multiplexers to select signal sources, and flip-flops. Because these were programmed by the user, the routing had to all be in place on the chip. This was done by placing metal traces all over the chip but keeping them unconnected. At junctions between unconnected traces were transistors that could be turned on by setting a bit in the chip, thus creating a slow but definite connection between the traces. Unlike as ASIC, where the delay through a logic gate greatly overwhelmed the small delay for a signal to travel over a metal trace, the limiting factor in the timing for an FPGA was the delay through the routing traces because each jump from one trace to another occurred through a slow transistor.

Figure 2

Figure 2: Field Programmable Gate Array (FPGA) architecture

Because routing resources were limited and slow in the FPGA, the logic blocks needed to have enough logic to logic to create small state machines. Each logic block had flip-flops to reduce setup and hold times within the chip, meaning that there was an abundance of flip-flops even if the design didn’t require them all.

Just as with ASICs, several FPGA architectures were developed, but this architecture was the one that won out and was adopted by all FPGA vendors. The FPGA architecture was a very inefficient use of silicon, but it was the only way to make a large, fully programmable chip. This meant that the cost per piece was exorbitantly high – in the hundreds of dollars – but there was no NRE whatsoever. Un-programmed FPGAs could be purchased in quantities of one, programmed on the desktop, and immediately used in a system.

The Structured ASIC to the Rescue?
As more customers used FPGAs, they could be produced more and more cheaply and their prices came down dramatically. Suddenly the per-piece prices were competitive with gate arrays and offered the advantage of easy programmability and very fast turnaround time. Gate array sales dropped off and ASIC vendors decided to focus on the standard cell, which had higher profit margins anyway. The gate array died.

What the ASIC vendors had not foreseen is that as FPGA volumes and transistor densities continued to increase, FPGA sales would begin to eat into standard cell sales. ASIC design starts were at around 12,000 per year only a few years ago, but dropped to under two thousand last year. A few years back ASIC vendors came up with a so-called solution – the structured ASIC, whose architecture is shown in Figure 3. Look familiar? ASIC vendors figured they could lure FPGA customers back to ASICs by creating a familiar-looking device. The irony of this is that – back in the early days of FPGAs – the ASIC vendors scoffed when the FPGA vendors tried to lure ASIC customers by saying that an FPGA was just like a gate array ASIC – hence the name.

Figure 3

Figure 3: Structured ASIC architecture

Comparing Structured ASICs and Gate Arrays
Structured ASIC vendors have gone to great lengths to compare their products to FPGAs to show their advantages. Structured ASICs, they claim, are just like FPGAs only faster, less power hungry, and cheaper per piece. Kind of makes sense. Until you realize that they’re making the wrong comparison. Let’s compare the structured ASIC to its forefather, the gate array, a device that we already know was killed by the FPGA. The FPGA architecture works great for an FPGA because of its routing limitations. But the structured ASIC has no such limitation and so the architecture is not only inefficient, it’s unnecessary. The structured ASIC has even worse utilization, requiring more silicon area for the same function as a gate array.

Structured ASIC vendors are also saying that the FPGA-like architecture makes it easier for customers to translate FPGA designs to a structured ASIC; the logic mapping is easy because of the common architectures. There are two reasons that this argument doesn’t make sense. First, logic designers use hardware description languages like Verilog to design their chips. No one designs a chip in terms of logic gates or logic blocks. Synthesis software takes the high level description and turns it into lower-level gates and blocks. Synthesis software can take a design and fit it into a different chip architecture in a matter of hours or minutes. So it makes no difference that the chip architectures are similar. In fact chip architecture is nearly invisible to the designer.

The second reason that this argument makes no sense is that very few FPGA customers ever turn their FPGAs into ASICs. Sure it reduces the per-piece cost, but it requires a large up-front NRE. Yes an ASIC will have better timing, but the FPGA timing better be good enough to use in your system in the first place. Better timing won’t be useful unless you can speed up your entire system, not an easy task. Ironically, FPGA vendors from time to time have had programs to turn FPGAs into ASICs, but few customers took advantage of these programs. I believe the programs were put in place not to produce ASICs, but to wean ASIC customers to FPGAs and provide them with a safety net �" if the FPGA didn’t turn out well they could always quickly turn their design into an ASIC. But the FPGAs did work out. Now ASIC vendors are using the same story to wean FPGA customers to ASICs. And according to LSI Logic, the story isn’t producing customers or revenue and so they rightly dropped their RapidChip structured ASIC.

The only exciting new thing about the structured ASIC was all the hype produced around it – hype that blinded the ASIC vendors and enticed venture capitalists and market analysts. But customers did the math and, to quote Yogi Berra, they “stayed away in droves.? Producing a poorly utilized, high cost chip using an inefficient architecture is unlikely to produce much revenue.

If there is a solution for ASIC vendors, it’s to simply bring back the gate array. After that it’s a question of economics. If someone out there knows how to reduce the NRE and the turnaround time for an old-fashioned gate array, that will be interesting, and I think customers will be interested too.

Do you have a product that you think qualifies for worst semiconductor product? If so, send it to me at If I get enough interesting responses I’ll put them into another article.

Bob Zeidman is the president of Zeidman Technologies (, a company that develops software tools for embedded system design. He is also president of Zeidman Consulting (, a contract research and development firm. Among his publications are technical articles on hardware and software design methods as well as three textbooks �" Designing with FPGAs and CPLDs, Verilog Designer's Library, and Introduction to Verilog. Bob holds two patents and earned bachelor's degrees in physics and electrical engineering at Cornell University and a master's degree in electrical engineering at Stanford University.

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