Published on April 15th, 2006

A new route to improving time-to-yield

Improving yield is key to the profitability of high volume memory chip design, but there is a better way to enhance time-to-yield than just throwing design for manufacturing tools at the problem.

Achieving optimum yield is an increasingly important factor in chip design. As the industry moves to 90nm and 65nm production and lower process geometry designs, realising optimal yield as quickly as possible is crucial to the profitability of a design project.

For high-volume DRAM and flash memory devices, improving time-to-yield is a fundamental goal; the ability to achieve just a few percent better yield in the same design time can equate to millions of dollars in increased profit. The numbers are such that designers will actually spin mask layers to achieve even a 1 per cent improvement in yield.

The key challenge in optimising yield is balancing this requirement with the equally critical need to minimise area, die size, and design iterations. The raft of Design For Manufacturing (DFM) tools emerging at the moment is a testament to the growing focus on this issue and the search for an effective solution.

However, DFM is only one approach to addressing yield enhancement. There is one critical area that offers the key to successfully optimising the yield of a device – routing.

The majority of routing tools offer only a limited solution to realising yield and, as a consequence, post-processes have been introduced to deal with the issue, resulting in iterative loops while an optimum solution is converged upon. Critical factors for enhancing yield include the ability to adhere to optimal spacing rather than minimum spacing. The ability to optimise the track widths, metal density, and via structures can – with the right tools – all be tackled during the routing of the design.

In traditional Manhattan-based grid routing, the design is broken down into individual sub-blocks or switch boxes which are then routed. These are then linked together for the final route. While this approach is, on the whole, reasonably quick for purely digital designs, converging on the optimum solution typically takes many iterations. This is a complex task, and the majority of the information about the nets and how they interact has to be dropped in order to perform it.

Moreover, these grid-based tools struggle to optimise the routing between different switch boxes, and across the chip. For memory designers trying to optimise memory cells with the columns and rows of the interconnect and the I/O cells, this is a major problem. When the tracks lie on the boundary of a switch box it can be difficult to optimise the layout, since these areas are square and not suited to the extreme aspect ratios of the area, which is often 30 times as wide as it is high.

A better approach to routing offers a solution to meeting the needs of the memory designer working with leading-edge process technology.

Shape-based routing optimises high volume designs for increased profit. It uses a technique where each net is routed with an algorithm that searches for the least cost routing but also factors in other important design rules. A major advantage of this approach is that it allows all the data from the design database to be used while the net is being routed, so that signal integrity and DFM issues can be included the first time. While the process is fully automated, it still allows the designer to focus on particular areas and intervene manually to attain the optimum routing in the first pass. This shape-based routing method also allows tracks to be pushed aside to squeeze through and achieve the best possible density within the DFM and SI constraints, producing the smallest possible die for the highest possible yield.

Another major benefit of the shape-based approach extends into floor planning, where it can be used to prototype the wiring and provide estimates of the congestion and parasitic estimations. It can then deliver the final routing once the floorplan and cell designs have been completed, allowing the cell design and floorplan groups to work in parallel, with confidence that the final routing will match to the estimates from the prototype.

The founders of shape-based tool company Pulsic ( have been working with the technology for twenty years. Within the last five, Pulsic has delivered the Lyric family of tools to the industry's top memory manufacturers. These have taken shape-based routing on from its initial capabilities to add signal integrity, design rule checking and DFM capabilities, plus the ability to handle engineering change orders simply and easily through the push-aside feature.

These are the key factors that have attracted engineers from many of the leading memory companies such as Elpida and Hynix – customers who are developing some of the highest volume silicon devices on the planet – to use Lyric to optimise their designs.

Elpida had earlier identified that the most time-consuming part of its design cycle was the routing of the peripheral logic, where rows of standard or custom cells are positioned beside memory cores in the design. Having identified this area for improvement and evaluating how the Pulsic solution addressed this issue, Elpida began using the Pulsic tool in its 0.11µm flow for DRAM designs.

Shape-based routing brings significant advantages to memory designs on leading-edge processes, allowing designs to be routed faster and more effectively than with traditional tools. By avoiding multiple iterations, reducing design times and enabling minimum area at the lowest cost, this approach is offering designers working at nanometer processes a fast new route to optimum yield.

Mark Waller, co-founder and Vice President of Research and Development at Pulsic (, was a key developer and project leader of IC Place and Route Research at Zuken-Redac Systems Ltd.

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