In IC design, parasitic extraction is the process by which layout geometries are analyzed and converted to equivalent circuit values for simulation and verification of electrical performance. This modeling of “as implemented” IC circuitry is critical to the verification of such performance parameters as timing, signal integrity, and power.
To achieve the highest level of accuracy in electrical circuit simulation requires a full implementation of Maxwell’s equations to compute the electrical field at each point in a 3D space. Tools known as “field solvers” create a full representation of IC circuitry by solving Maxwell’s equations, then using the results to provide a circuit model at the highest degree of accuracy possible. However, due to their extreme runtime requirements, field solvers have historically only been used in conjunction with test chips to calibrate “production” extraction tools that provide higher performance and throughput, but less accuracy.
These production extraction tools employ a simplified set of heuristics, or rules, to perform the layout analysis and create the circuit model. Underlying transistors are represented abstractly at the gate level or transistor level, and their performance is assumed based on the gate or transistor model. Such rules-based tools generally run up to three orders of magnitude faster than a field solver, and provide a sufficient level of accuracy for most of the extraction process to ensure adequate performance modeling of the final chip. However, detailed extraction using a field solver must sometimes be performed on the interconnect wires to determine the parasitic capacitance between the wires. This adds time to the extraction process, negating some of the benefit of using rules-based extraction tools.
At the 32/28 nm node, decreasing space means field effects have more influence on neighboring structures, and these effects extend over a greater number of adjacent transistors. What were second-order device parasitics with minimal performance impact have now become first-order parasitics capable of degrading performance or generating operational failure. The extraction process now needs to include the properties of the individual transistors themselves, which demands a higher level of accuracy. With a greater proportion of the layout requiring this more precise extraction, rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance.
Field solvers are the only technology that can provide the needed degree of circuit accuracy at the 32/28 nm nodes. However, as mentioned, their runtimes have generally prohibited their use for all but individual cells or very small blocks. In addition, existing field solvers are not constructed to scale to today’s large designs with billions of transistors.
Some companies have attempted to resolve these issues with extraction tools that contain both a rules-based engine and a field solver. The premise is to use the rules-based engine in less critical areas of the layout, switching to the field solver when high accuracy is required. The flaw in this approach is that a designer must specify what constitutes a “critical” area, either through explicit designations or by the use of some heuristics. However, it is virtually impossible for the designer to know in advance which areas of the layout will prove critical to performance. Making the wrong choice can lead to some critical areas being excluded. These “outliers” could be the cases that result in operational failures.
What is needed is an entirely new extraction approach incorporating a field solver constructed to run at commercially acceptable speeds. Such a field solver would need to incorporate extremely efficient computing algorithms, while also being able to scale effectively to take advantage of today’s multicore CPU configurations. A field solver that can maintain accuracy in the 5% range while providing a runtime improvement of several magnitudes over traditional field solvers would allow field solver technology to be used on the entire design, providing greater overall accuracy without significantly increasing overall turnaround time.
But of course, that’s not all. Users don’t like disruption, either in their tools or their workflows, so any such extraction tool should also be integrated with existing tools and interfaces, and require only minimal changes to extraction rule decks. For ease of use, the application of the field solver should be transparent, requiring no direction or manipulation by the users.
Implementing a fundamentally new software architecture without changing the way a tool operates is always a challenging proposition. But in the case of parasitic extraction, it’s one that is necessary if we hope to maintain the performance of chips as we move closer to the limits of nanometer technology. Extraction tools using fast, scalable field solver technology will enable us to develop advanced node designs in market timeframes without sacrificing performance.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015
Mesa, Arizona March 15-18, 2015
Santa Clara, CA May 6-7, 2015
Encore at the Wynn Las Vegas, NV May 19-22, 2015