Evolution, whether biological or technological, is a never ending process. When faced with a new challenge or opportunity, we change to meet the new reality. Over the decades, we have seen several marked periods that brought on rapid technological change in the IC design and verification flow. Today we are clearly approaching new challenges that are spurring innovative, evolutionary change along the entire design chain. These challenges represent an inflection point, a disruptive change that will lead to advancements in tool capabilities and design flows.
One emerging improvement to design flows for the 28nm node is better technologies for reaching manufacturing closure. Starting at 45/40nm, the increasing complexity of DRC and DFM rules began to stress traditional physical design flows. The consequences of the growing manufacturing complexity leads to lost market windows or poor manufacturability because of the growing disconnect between place and route and sign-off physical verification.
Place and route tools typically use simplified DRC and DFM models during implementation, which is an accuracy versus runtime tradeoff. Starting at the 45/40nm node, there is a trend towards increasing complexity and number of rules that need to be honored. In fact, there are some rules that cannot be even described by the simplistic place and route modeling techniques. In addition to the modeling inaccuracies, the growing use of IP has exacerbated the problems with outdated rules or rule mismatches that are only revealed late in the design flow.
As a result, the number of DRC and DFM surprises found during signoff verification is increasing significantly. Further, the DFM enhancements such as CMP, LFD, and CAA which used to be done after the layout is complete are now starting to affect the traditional design metrics like timing, power and signal integrity. Going into 22nm and beyond, this problem will get even more severe as the limitations in light lithography require more design correction to account for the variability between the “as-drawn” and “as-built” shapes.
So, for 28nm and below, we need an architecture that can address these late stage manufacturing surprises much earlier in the flow for a true correct-by-construction approach. There are some claims of such solutions, but the questions to ask are these: are the analyses actually signoff quality? Can the place and route tool fix the violations in an automated and intelligent fashion? Can manufacturing closure be achieved in a holistic fashion without affecting the timing and power closure?
It is time again for EDA to evolve in order to maintain the historical pace of node transitions. Designers need a completely consolidated flow that eliminates the traditional design-then-verify iterations used today. The next generation of solutions must reduce time to manufacturing signoff, and therefore time to market and overall development costs and effort.
Sudhakar Jilla is the marketing director for place & route products at Mentor Graphics. Over the past 15 years, he has held various application engineering, marketing, and management roles in the EDA industry. He has been previously responsible for the rollout of several market leading products and initiatives such as Pinnacle, Olympus-SoC, Design-for-Variability at Sierra Design Automation and Physical Compiler, Galaxy-SI at Synopsys. He holds a Bachelors degree in Electronics and Communications from University of Mysore, a Masters degree in Electrical Engineering from the University of Hawaii, and a MBA from the Leavey School of Business, Santa Clara University.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446
Grenoble, France March 9-13, 2015
Mesa, Arizona March 15-18, 2015
Santa Clara, CA May 6-7, 2015
Encore at the Wynn Las Vegas, NV May 19-22, 2015
San Francisco, CA June 7-11, 2015