A year ago it was all about developing hardware at the leading edge of Moore’s Law. Now the focus is on developing software.
In a span of months the EDA industry has pointed its headlights in an entirely new direction. And while work will continue at 28nm, 22nm and beyond for smaller features along the classic Moore’s Law road map, all three of the major EDA vendors are plotting distinctly different courses that focus heavily on software.
Here’s a look at some of the new and developing approaches:
While none of the Big 3 will abandon their existing markets and flows, all see limited growth—as well as interest from investors—in just the classic EDA market. And they see an increasing role for software in SoC design.
Of the three, the most radical shift is at Cadence, which has been largely in retrenchment mode over the past two years. Cadence is calling its new direction “EDA360,” and what’s different—at least in the initial announcement—is the starting point for thinking about the problems that EDA needs to solve. Rather than rely on tools to create the best SoCs, and then build software stacks to run on the hardware, the company is looking at the application software and middleware first, while the hardware becomes more of a generic application platform. According to the plan, the software should be able to reconfigure the hardware as necessary.
John Bruggeman, chief marketing officer at Cadence, said this is the strategy being used with great success by both Apple and Google. Rather than the platform dictating how the applications run, the applications are dictating the platform. But making that strategy work on a mass scale requires a different way of looking at the complexity in design, he said.
“This is an integration problem,” said Bruggeman. “At 65nm and 40nm, for every $1 spent on IP it requires $3 to integrate it into the SoC. The challenge is getting the $3 integration cost down. The problem of integration is all about profitability.”
The terminology that keeps popping up in Cadence’s 28-page blueprint is “realization.” There is system realization, SoC realization and silicon realization.
According to the document: “With an application-driven system realization approach, developers can start by envisioning the application. They can then design at the system level as far as possible, work down to the software, and finally build or buy the hardware. The application-driven approach will help close the profitability gap by addressing cost, time to market and quality.”
Mentor already is looking well beyond just the chip. Its Nucleus RTOS and Linux tools strategy are playing a big role in the company’s move into a variety of communications devices. Case in point: The deal with Freescale that was announced this week to provide specific features in the Linux to support the silicon is a first for an EDA company.
“For evaluation purposes, the user gets a version of Linux that will be optimized by Mentor Graphics and Freescale,” said Shay Benchorin, director of marketing for Mentor’s embedded software division. “When the company doing the evaluation is ready to go commercial, we build on that. In the past, if you changed software or development tools you had to change the product. This is a new approach for users. You can evaluate the silicon and make sure it’s optimum for your use, then ramp to production in the shortest amount of time. The first set of tools will be for performance evaluation. The second set will be for debug, improving performance and optimizing power.”
Mentor also sees this strategy working well with its Nucleus RTOS, particularly with a multicore chip where one core can be running Android and the second can be running Nucleus. Add in virtualization software and each core can do many tasks that are separate, or which are integrated but run concurrently across multiple cores.
Mentor’s acquisition of Valor last month also moves the company well into printed circuit board-level design, as well. Valor has its own Design for Manufacturing (DFM) tools in addition to manufacturing execution and control software (see “EDA Extends Board Design into Manufacturing”). This essentially allows Mentor to control both the design and manufacture of a complete PCB. Add to that mix Mentor’s acquisition in 2009 of Flowmetrics, which helps model thermal challenges faced when designing the packaging in which chip dies reside.
At an even higher, pre-hardware or software partitioned architectural level, Mentor also has tools for system modeling that interface with mainstream requirements packages like Doors.
Synopsys is well along in its strategy of concurrent design to speed up time to market. Whether the software ultimately drives the hardware or vice versa doesn’t really matter with Synopsys’ approach. What does matter is that they both get designed concurrently.
As Aart de Geus, chairman and CEO of Synopsys, said in a recent interview: “As a percentage of our business, classic EDA is shrinking, but this is not a case of ‘classic EDA doesn’t grow.’” For example, in the past, EDA companies added front-end RTL synthesis and design tools with timing and power closure to improve the productivity of chip designers. Next, efficiencies were found in the back-end of the process by adding physical design with extraction and Design for Manufacturing (DFM) and Yield (DFY) tools. Today, EDA vendors are improving the value of system-level design with architectural tools.
Synopsys’ recent acquisitions in the virtual protoyping market are good examples of this trend. In recent months Synopsys added CoWare and VaST to its collection of existing virtual prototyping tools, having acquired Virtio several years ago. Virtual prototype tools are necessary to create the executable models needed by programmers and software engineering who create software applications for electronics, especially in the short time to market markets like mobile phones.
The Bigger Picture
Some industry executives say the automated chip design and manufacturing industry is being absorbed back into the semiconductor supply chain. Such advocates point the fact that two of the three major EDA tool vendor CEO’s either lead semiconductor industry organizations – like GSA – or hold seats on the board of directors for major semiconductor (not EDA) companies.
In all respects, EDA companies are moving up the electronic development chain to embrace a full system-level or total platform market. This is a move beyond just tools to create and manufacture today’s high complex chips – still the mandatory hardware “system” for any electronics. These systems-on-chip (SoC) designs have become more prevalent thanks to engineering innovation and the consumer push for higher performance, lower power and less expensive products. Indeed, the SoC hardware has become the given, the commodity in the electronic product equation. What, then, is the differentiator?
To answer that question, one must consider three major trends. One is the application of the problem-solving approaches, techniques and algorithms developed in the EDA market to industries that have a growing electronic component, such as medical, industrial and automotive. (see “Is EDA Still EDA?”)
Another important trend is the movement up the electronic product chain to include the design and manufacture of – not only the SoC – but also the chip package design and pin layout to even the printed circuit board on which all the electronic components reside. Mentor is not alone in extending it reach toward the board level market. Cadence has tools for the design (not manufacture) of PCBs, too. The recent Cadence acquisition of Taray enables the design of multiple FPGAs on a single board design. Synopsys’ acquisition of Synplicity-Hardee and then Prodesign give it a strong tool suite in the design of FPGA for rapid prototyping and hardware modeling.
Perhaps the most telling trend is toward the incorporation of software operating systems and applications as the future differentiator in both chip and even board level products. Few can doubt that the EDA market is definitely shifting direction toward a system-level, software rich platform. Who will win or lose as these platforms continue to emerge in new electronic markets is the real question. But for now, at least, there’s plenty of change to watch—and ultimately to judge over time.
Ed Sperling is Contributing Editor for Embedded Intel® Solutions and the Editor-in-Chief of the “System Level Design” portal. Ed has received numerous awards for technical journalism.
John Blyler is the Editorial Director of Extension Media, which publishes Chip Design and Embedded Intel® Solutions magazine, plus over 36 EECatalog Resource Catalogs in vertical market areas.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
San Francisco, CA December 13-17, 2014
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015
San Francisco, CA June 7-11, 2015