Published in June / July 2010 issue of Chip Design Magazine
A PHY for all Seasons: MIPI® M-PHYSM Takes Center StageWith Mobile applications pushing the limits of performance—it is time to introduce a new PHY
The curtain is up and the M-PHY specification is taking center stage. It is positioned to handle the many different roles required for a faster, more reliable, physical interface layer (PHY) on mobile devices. The script for the M-PHY specification was written inside the Mobile Industry Processor Interface (MIPI) Alliance by a working group made up of member companies. It was set up to expand the capabilities of mobile devices by defining interface standards that will revolutionize the capabilities of the coming generations of mobile products. Faced with an explosion of mobile multimedia devices with an ever-increasing demand for faster throughput, the mobile industry—through the MIPI Alliance—has defined the ultimate PHY. This PHY is capable enough to handle the demands of mobile devices and seemingly capable of moving into several other key application areas as the PHY of choice.
The mobile market is exploding with device after device ranging from smart phones to e-readers. These portable products are impacting almost everyone every day. A total of 1.2 billion mobile phones were shipped globally in 2009. The expectation is that this number will nearly double to 2.25 billion by 20141. The announcements of new products also continue. The introduction of Apple’s iPad is just another example of the excitement around this market. Because the portable consumer market is driven by keeping costs and power low while improving function, controlling cost is critical to the overall success of a product.
By elevating the price, the wrong mix of cost and function creates a product that can languish. It will produce only limited sales and never reach its full market potential. The development of industry standards is important in controlling costs. Standards guarantee interoperability, thereby allowing companies to independently accelerate development while giving systems integrators multiple supplier options.
MIPI and the M-PHY
The M-PHY specification is an essential part of the MIPI Alliance vision for new and more capable high-speed interfaces on mobile devices. Early on, members identified the need for a serial interface to support the ever-increasing data-bandwidth requirements of mobile devices. Now, those needs are pressed even further by the exp losion of digital content in video, social-media exchanges, and cloud computing. As a result, mobile devices require a faster physical-layer interface, such as the M-PHY, to remain a step ahead of the data-transfer requirements needed to give consumers the on-device response they need.
Fuelled by the success of the other MIPI standards now being deployed, the M-PHY specification is gaining momentum as it moves toward final approval as the newest MIPI specification. The MIPI D-PHY, a source-synchronous interface that is currently handling the interfaces between the application processor chip and the camera or display in a mobile device, has been especially successful. Even though the D-PHY is a capable interface, its synchronous nature has speed limitations (1 Gbit/s) that prevent it from handling the demands for higher data-transfer rates. The industry requires a more powerful PHY—one that offers asynchronous data transmission and addresses the speed and signal-integrity issues of high-speed chip-to-chip connections within an increasingly electromagnetic-interference (EMI) sensitive environment. This need is compounded by tighter form factors and the call to continuously minimize power dissipation. The M-PHY specification, which is slated to handle these high-speed issues, is becoming a silicon reality.
The M-PHY Plays Many Roles
Just like a versatile star, the M-PHY interface is talented enough to play many roles. When first envisioned, it handled the set of specifications that were already defined or in the process of being defined inside MIPI. Those specifications included the Camera Serial Interface (CSI), the Display Serial Interface (DSI), and a Universal Protocol (UniProSM). The CSI and DSI specifications are easily understood. They define the protocol interfaces between the application processor and a camera or display. For its part, UniPro is a comprehensive specification meant to act as a universal chip-to-chip protocol. It provides a common tunnel for other protocols. The M-PHY interface is designed as the primary physical interface (PHY layer) for the UniPro specification. The M-PHY specification has two signalling schemes that support both self clocking and embedded clocking. Additionally, it runs at both lower and higher speeds. The high-speed communication option makes the M-PHY interface the perfect vehicle for UniPro offering speed, power, and economy.
The first evidence of the M-PHY interface’s versatility emerged when the DigRFSM Alliance was assimilated into MIPI. That alliance had defined a specification between the baseband integrated circuit (BBIC) and radio-frequency integrated circuit (RFIC) for mobile platforms. This new specification describes the logical, electrical, and timing characteristics of the digital BBIC-to-RFIC interface. The M-PHY is ready to accept the role as the new physical interface.
The M-PHY interface was further recognized by JEDEC as an ideal physical layer for its highly anticipated Universal Flash Storage (UFS) specification. It defined a high-level interface that standardizes connectivity in an extensive range of diverse, non-volatile memory solutions that are currently being developed within the JC-64 Committee on Flash-memory modules. The M-PHY is an ideal player for the PHY-layer specification.
Building on this successful start, another subcommittee within JEDEC—the Low Power Memory J42.6 Subcommittee—is considering the M-PHY for yet another role as the physical layer for “future mobile.”
The M-PHY specification, when finalized, will provide a physical layer that shall always be used in combination with a higher-layer MIPI specification that references it. Any other use of the M-PHY specification is strictly prohibited unless approved in advance by the MIPI board of directors.
The Character of the M-PHY
The M-PHY is defined as a serial link. The overall objectives fall into this general requirements list:
- Low pin count with all control signalling handled in-band across the interface
- Supports both electrical and optical interfaces using low-complexity electro-optical signal conversion
- Optical-friendly electrical specification (sufficient timing flexibility, DC balanced coding scheme, etc.)
- Optimized for short distance (<10 cm) but suitable for long distance (m)
- Huge range of speed requirements: ~10 Mbits/s to ~6 Gbits/s
- Power-efficient throughput adaptation using burst mode
- Clocking: shared or non-shared reference clocks
- Independent of foundry process
- EMI friendly
- Multiple transmission modes for better power efficiency
- Multiple transmission-speed ranges/rates for varied application needs and mitigation of interference problems
- Fixed transmission rates for high-speed mode, but flexible for low-speed modes within specified ranges
- Multiple power-saving modes in which power consumption can be traded off against recovery time
- Symbol coding (8b/10b) for spectral conditioning, clock recovery, and in-band control options for both the PHY and protocol level
- Configurability to reduce cost and tunability for best performance
The Stage and Script
There are two fundamentally different types of M-PHY interfaces. They are denoted as Type-I and Type-II, depending on which signalling scheme is used (see Figure 1). For low-speed operation, Type-I employs pulse-width-modulation (PWM) signalling. In contrast, Type-II uses system-clock synchronous non-return-to-zero (NRZ) signalling. Type-II requires a shared reference clock between the two ends of the line. Yet Type-I is able to operate with independent local clock references on each side of the link. Although Type-I and Type-II aren’t interoperable, implementations may support both types in order to enable hardware reuse. In other words, one M-PHY implementation can service multiple applications and connections inside a mobile device.
Figure 1: This graphic depicts the M-PHY Type-I and Type-II clocking architectures.
Working the Media
Of course, part of the motivation for specifying a more capable PHY has to do with adding exciting new features. But it also stems from the opportunity to improve the reliability of mobile devices. Connecting two sides of a clamshell phone, for example, requires an interconnect that’s flexible enough to withstand mechanical stressors at transfer speeds that are high enough to satisfy application requirements. In addition, it must provide signal quality that is good enough to ensure reliable reception. Finally, this PHY must dissipate minimal power and contribute little EMI.
Optical links offer robustness and mechanical flexibility along with superior EMI and noise immunity. Some mobile devices have complex hinge (flip-side-twist) mechanicals. These hinges give viewers control over their view angle, which is very important when the display is smaller and it’s necessary to reduce eye and neck stress. One example of a complex two-axis movement is shown in Figure 2. There, the first access acts like a flip phone and the second allows adjustment of the display viewing angle. The data rates across these hinges and the susceptibility to mechanical failure limit the number of copper connections that cross the hinge and the materials that can be used to maintain reliability.
Figure 2: Advanced mobile devices have multiple-axis movements that add mechanical stress to the interconnect between the display and processor.
Whether copper or optical fibre is used, the M-PHY specification defines a flexible architecture that allows the implementer to support high data rates at minimal power and cost. The challenging aspects of delivering high-definition streaming video—loading gigabyte-wide movies (from the Internet) in an ‘everyone, everywhere, seamless wireless connection to surrounding devices and services’—will only come from an optimized chip-to-chip interface like the M-PHY.
The Final Act
The final necessary ingredient for the successful deployment of the M-PHY specifications is a healthy ecosystem of companies that can develop, test, demonstrate interoperability, and deliver the M-PHY infrastructure to market. The collaboration between suppliers that can fill these roles is the final act in realizing the ultimate benefit of all of the work done by so many contributors in the MIPI Alliance. One of the key components of a vibrant ecosystem, are the IP providers that can build and deliver the M-PHY subsystem, thus allowing rapid adoption to take place. The very nature that makes the M-PHY interface unique—namely its versatility, many architectural options, and ability to address many different applications—makes a one-size-fits-all IP approach a self-defeating proposition.
This is different from other standards like PCI Express, SATA, or DDR, in which a single architecture can be ported to many process nodes to effectively address the requirements of thousands of customers. For the M-PHY to fulfill its potential of being an optimized solution for applications in which power, area, and total cost are all parameters of paramount importance, a cookie-cutter approach will not do. Successful MIPI adopters will be those who can partner with an M-PHY IP vendor that can provide shrink-wrapped, silicon-proven yet customizable, high-quality differentiated IP at a reasonable cost.
For example, Mixel® and Japan’s Graphin Co. Ltd. plan to support the MIPI M-PHY ecosystem by building a “Golden M-PHY” IC to be used in Graphin’s evaluation systems. The same “Golden M-PHY” IC will be made available to support the M-PHY interoperability and testing requirement of the MIPI ecosystem. Mixel is also collaborating with the UK’s Nanotech Semiconductor, which chairs the Optical M-PHY subgroup, to support the MIPI M-PHY optical ecosystem. Mixel employs what it dubs a "Legorithmic" approach, which enables it to effectively develop efficient, shrink-wrapped MIPI IP based on its silicon-proven building blocks to meet the large set of M-PHY flavors that will be required for the variety of M-PHY applications.
Today, every mobile device—together with every bandwidth-hungry new application developed to run on those devices and every new capability that pushes the limits of performance—indicate that it is time to introduce a PHY to meet these challenges. The curtain is up and M-PHY is ready to go—a PHY for all seasons.
1. ABI Research, http://www.wirelessandmobilenews.com/ 2009/12/12-billion-mobile-devices-shipped-in-2009-says-abi-research.html
Ashraf Takla is president and CEO of Mixel Inc., which he founded in 1998. Before Mixel, Takla was director of mixed-signal design at Hitachi Micro Systems. He also worked at AMI and Sierra Semiconductors. Takla has 30 years of experience in analog and mixed-signal design. He holds five patents. Takla received his BSEE and MSEE degrees from San Diego State University.
George Brocklehurst, marketing director for consumer at Nanotech Semiconductor Ltd. He holds two chairing roles within the MIPI Alliance; Vice Chair PHY WG and Chair Optical SG. Brocklehurst has 10 years product/market development experience in the semiconductor industry. He holds an MBA from Southampton Solent University and a bachelor’s in electrical engineering from Southampton University.
About the MIPI Alliance
The Mobile Industry Processor Interface (MIPI®) Alliance is an open-membership organization that includes leading companies in the mobile industry that share the objective of defining and promoting specifications for interfaces in mobile terminals. MIPI Specifications establish standards for hardware and software interfaces typically found in mobile terminals. By defining such standards and encouraging their adoption throughout the industry value chain, the MIPI Alliance intends to reduce fragmentation and improve interoperability among system components, benefiting the entire mobile industry.
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