Consumer and industrial electronics system suppliers continue to push the limits of integrated-circuit (IC) technology. Their goal is to provide more functionality in smaller, more portable and power-efficient packages. Yet achieving manufacturing signoff is getting more difficult at each node. Significant limitations are being encountered due to the continued use of 193-nm lithography steppers, which have reached the limits of their resolution capabilities (see Figure 1). To compensate for these limitations, designs are becoming subject to a growing set of complex design rules (DRC) and design-for-manufacturing (DFM) constraints. At 40/28 nm, the number and complexity of these rules has increased many times. This trend will continue as the industry marches toward 20 nm and below.
The growing challenge of manufacturing closure results in late-stage surprises, more iterations to fix violations, the inefficient use of engineering resources, and overall longer time to market. The reasons for this include: the growth of mandatory DRC/DFM requirements, disconnects between the signoff models and those used during design, outdated routing algorithms, inability to perform automated fixing, and inefficient file transfers between design and signoff tools. The industry needs a solution that addresses all of these issues in a holistic and efficient manner. A design engineer should be able to guarantee that the implementation is both timing closed and DRC/DFM signoff-clean—without having to leave the place-and-route environment.
Figure 1: The gap between the wavelength of light used for lithography and the required feature resolution is responsible for the growing number and complexity of design and manufacturing rules to which designs must adhere.
Sources of Design-Closure Problems at Advanced Nodes
To ensure that physical designs can be reliably manufactured, foundries are greatly expanding the number and complexity of design rules and DFM requirements at advanced nodes. The number of DRC and DFM rules has roughly doubled between the 90- and 32-nm nodes, depending on the foundry (see Figure 2). The rule complexity, which is measured by the number of operations required to verify the rules, has grown even faster (as shown by the red bars in Figure 2).
Figure 2: The number of design rules and the complexity of those rules have risen steadily at each process node, leading to growing problems in design closure.
DFM checks, which used to be voluntary, are now becoming mandatory just like traditional DRCs—with the type and complexity of checks being foundry dependent. DFM violations can cause issues ranging from chip failure to reduced reliability and decreased performance. If they aren’t made carefully, however, changes to improve manufacturability can reduce performance, increase power consumption, or otherwise compromise the design. Therefore, it’s extremely important to be able to make smart tradeoffs when fixing DFM violations in order to ensure high yield without over-designing. Unfortunately, the current design-then-verify flow is not adequate to address these new challenges for a number of reasons.
Pitfalls of the Traditional Design-Then-Verify Flow
Design-then-verify refers to the traditional methodology of doing design in isolation of signoff requirements. The problem with this approach is the disconnect between design and verification models. As a new process technology (node) matures, the foundry’s design-rule files—typically expressed in Standard Verification Rules Format (SVRF)—are constantly updated to address new issues as they are discovered. Consequently, the signoff models are intrinsically the most accurate and complete representation of actual manufacturing requirements. However, the technology files used in the place-and-route systems (expressed in LEF or similar syntax) are simpler. In addition, they are modeled for best accuracy versus runtime tradeoffs.
Typically, the place-and-route models are outdated and inaccurate compared to the signoff models. At 28 nm and below, there also are some rules described in SVRF that simply cannot be expressed in the simpler place-and-route modeling languages. During design, the router may therefore report the layout to be DRC/DFM-clean even though the signoff physical verification tool will later uncover violations. Even subtle mismatches can cause an unmanageable number of violations late in the design cycle and lead to time-consuming iterations between design and verification environments to fix them. As the industry goes into advanced nodes, the gap between the design and verification models is increasing. The result is a growing number of late-stage surprises at signoff.
Another problem is the architecture of traditional routers. These routing algorithms are based on simplified DRC/DFM models during global and detail routing phases. They use more accurate models during the final routing or search-and-repair loops. For previous nodes, this approach worked adequately because the number of violations remaining after detail routing was typically in the tens to hundreds of errors. At 40 nm and below, however, the number of violations has exploded to thousands for the reasons discussed previously. In this scenario, the search-and-repair methodology becomes untenable because the design has become “locked in,” there are too many issues to fix, and the process becomes lengthy and non-convergent.
Lastly, the impact is being felt from various DFM enhancements including chemical-mechanical polishing (CMP) for planarity, litho-friendly design (LFD), and critical-area analysis (CAA). Although such enhancements used to be post-processing steps, they are now starting to affect the traditional design metrics like timing, power, and signal integrity. For example, adding metal fill or moving wire edges to meet manufacturing requirements can cause degradation to timing and SI as the parasitic interactions change.
The next pitfall of traditional manufacturing closure is that the current methodology of manually fixing the DRC/DFM signoff violations is broken and cannot scale for the advanced nodes. A handful of violations can be fixed manually without affecting the design too much. But when there are thousands of violations, manual fixing is not feasible. It also is error prone. Aside from the delays and tedium of making the individual repairs, it’s simply not possible to make the changes needed for manufacturability without impacting the design in a major way. In addition, the changes introduced manually will often result in new DRC or DFM violations, leading to an endless loop of contradictory changes.
Finally, to make matters even more painful, the traditional flow is characterized by huge and lengthy ASCII file transfers between the implementation and signoff environments for each iteration. As design sizes increase, a flow based on ASCII file transfers cannot scale and becomes a big time sink.
Today, the common workaround to bridge the disconnect between implementation and signoff is to build in larger timing margins and overly restrictive DRC rules. This approach forces over-design, which affects both die size and performance—partly erasing the advantage of migrating to a smaller node. At 28 nm and below, the manufacturability restrictions are expected to become so tight that designers will not be able to fix DRC/DFM problems in post-layout processing alone without significantly impacting other design requirements. If the traditional approaches to physical design are having trouble at 28 nm, they will be completely inadequate at future nodes.
Manufacturing Signoff in Place-and-Route
For 28 nm and below, designers need a platform that integrates physical design and manufacturing signoff for a true correct-by-construction approach. The critical criteria that determine an effective solution are the following:
Checking and fixing layout issues that relate to manufacturing is only useful if the tools have an accurate model of the target manufacturing process. These models vary for different manufacturers and for each process line (40 nm, 28 nm, bulk CMOS, low-power CMOS, SOI, etc.). A solution for physical sign-off in place and route should use the same golden SVRF rules used in standalone physical signoff tools to eliminate non-convergent iterations between tools. It should include the full suite of manufacturing closure facilities—including DRC, LVS, litho simulation, CMP modeling, and smart fill—to ensure that all aspects of design for manufacturability are addressed comprehensively.
Figure 3: This product promises to enable the designer to invoke Calibre physical signoff capabilities directly within the Olympus-SoC place-and-route environment. Manufacturing issues may then be found and repaired during design.
Automatic Fixing Is Critical
Rather than manually fixing annotated violations, the solution should provide automated and intelligent prevention and repair capabilities. The DRC/DFM violations should be addressed in the full context of the traditional design metrics. This is the only way to ensure that all of the manufacturability issues are addressed without introducing new ones or degrading the performance of the design to the point where it is no longer competitive. It is also imperative that the place-and-route system use the actual signoff SVRF models during implementation to eliminate modeling discrepancy violations.
Performing true signoff verification in the design environment allows designers to use realistic margins and attain higher performance and lower power while accounting for all manufacturing issues—without extending time to market. The new solution will also enable much more efficient use of precious engineering resources.
The EDA industry is taking steps in this direction. For example, the Calibre® InRoute product allows all Calibre rule decks and analysis engines to be invoked directly within the Olympus-SoC place-and-route environment to identify DRC/DFM violations much earlier in the flow. They are then automatically fixed by Olympus-SoC. In this way, the manufacturing signoff process is predictable and accelerated, delivering higher-quality designs and faster time to market (see Figure 3).
Significantly, the product allows the Calibre engines to be invoked at the block or full-chip level whenever the designer chooses to perform a signoff check. Because Olympus-SoC supports a virtually unlimited number of concurrent modes and corners, it is able to optimize for all of the manufacturing signoff inputs from Calibre as well as all of the timing, signal-integrity, power, and area design targets at the same time. Unlike the old “search-and-repair” paradigm, designers no longer have to wait until the layout is essentially complete before starting the manufacturing closure process.
In addition, designs completed with Calibre InRoute promise to be inherently signoff-clean. They have already been verified by the same rules and engines employed during final verification. In addition, the product is supported by all major foundries because it uses the foundries’ golden signoff tool, Calibre.
How will integrated design and manufacturing signoff work in practice? Consider a case study with an actual 32-nm design that was placed and routed and then analyzed for DRC violations with the native place-and-route DRC checker during the “search and repair” phase. Based on this, the design appeared to be free of DRC violations. When analyzed with Calibre, however, nearly 1500 violations were uncovered in a complex end-of-line rule (see Figure 4). The violation was caused by incorrect spacing from the adjacent via pad. This was not found by the DRC checker during place-and-route because the technology file was outdated.
Figure 4: This end-of-line rule violation was found only during signoff verification.
These 1500 violations were annotated back into a layout editing environment for fixing. The change to the layout required new timing, signal-integrity, and power verification before another analysis with Calibre. Although the end-of-line violations were fixed after laborious manual efforts, the layout changes led to new violations that required additional iterations through the process.
Figure 5: The Calibre InRoute signoff analysis and automatic fixing detected and repaired this end-of-line violation without ever leaving the place-and-route environment. The image on the left shows the violation. The image on the right is the layout after the violation was automatically fixed in Calibre InRoute.
Using Calibre InRoute, the designer was able to perform SVRF-based signoff analysis by invoking Calibre directly within the Olympus-SoC place-and-route environment. All signoff violations were found and then automatically fixed by Olympus-SoC, which was driven by the comprehensive Calibre rule decks and engines operating within the inner loop of routing decisions. Because the violations were fixed in full context of the design, the timing, signal-integrity, and power profiles remained within specifications. All changes to the layout were DRC/DFM signoff-clean by definition without ever leaving the place-and-route environment (see Figure 5).
The demands of manufacturing closure at advanced process nodes exceed the capabilities of traditional physical design and verification tool flows. For 28 nm and below, designers need a solution that can address late-stage manufacturing surprises much earlier in the design process, thereby enabling a true correct-by-construction approach. It must support advanced DRC/DFM analysis and automated repair to produce designs that are optimized for all of the factors that ensure competitive, manufacturable, high-yield nanometer IC products. An integrated design and verification solution eliminates the traditional design-then-verify iterations required today. It also reduces time to manufacturing signoff and overall development costs and effort. The traditional manufacturing closure process, which typically takes weeks or months, can now be reduced to days.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446