Published on September 13th, 2010

Double Patterning Readiness: Technical and Economic Considerations

IC makers are approaching the resolution limits of single exposure 193 nm lithography with the shrink to the 22/20 nm technology node, which corresponds to a layout minimum pitch of around 80 nm. More than ever before, the solutions needed to enable device shrinks depend on software innovations such as computational lithography, design-to-manufacturing co-optimization and support for double patterning (DP). 

DP, while conceptually simple, greatly increases the complexity of layout verification and mask data preparation. Whether the industry is ready to deploy DP widely is less of a question of technical feasibility, and more an issue of economics, or “technology value.” The looming question about DP is whether it can be commercially successful and extendable to feature sizes even smaller than 22/20 nm. The answer is far from trivial, and with increasing manufacturing complexity, it is no longer dictated solely by the traditional scaling economics.

What are the technology and economic issues of DP? How does DP impact physical design and manufacturing? As with any interesting problem, the answer is “It depends”. A new process has the potential to be adopted if its costs are lower or if the functionality is superior at a given cost point. The advantage of double patterning approaches is that most of them are based on existing technology while a more traditional wavelength-scaling process (like EUV) introduces more uncertainty.

Using Restricted Layout Rules with DP

Layout restrictions certainly help make DP economically and technically more feasible, but they have been typically directed at the micro-structure of the layout. With double patterning approaches, one also needs to be aware of coloring conflicts which can quickly convert a fully compliant layout into an unsolvable layout. A coloring conflict occurs when adjacent elements in the layout cannot be assigned to different masks. The term coloring conflict comes from graph theory, which is used in the double patterning decomposition of a layout. This is in addition to the traditional need for a larger set of feasible topologies to avoid routing congestion.  When a congested situation is found, the traditional approach has been to apply a less aggressive placement, which will incur extra area that impacts cost directly.

In addition, restricted layout techniques do not guarantee that every independently-verified piece of IP remains DP compliant when placed next to another independently-verified layout. Sacrificial structures, which provide no electrical functionality and serve only to shield electrically active structures from process variations, are routinely inserted with limited analysis of the underlying processes they are trying to correct. This can result in missed opportunities for more compact designs where placement or routing can be adjusted to provide the same level of process protection without the need to waste die real estate.

Impact of Area, Power, Timing on DP

At smaller feature sizes we see increased manufacturing variability that can have a negative impact on active and stand-by power as well as timing. Since every DP technology has a different process variability signature and cost, it is paramount to assign the correct DP strategy to a given product. An example of this is the use of spacer DP technology in Flash memories. It is the right process technology for the right product, and trying to use any other DP technology would be less cost-effective.

The Need for DP Verification

Robust physical verification safeguards against the main pitfalls of a given process technology and it is critical to ensuring a rapid yield ramp. Traditional physical verification has been limited to describing fairly short feature effects (i.e., minimum distance, minimum width of a feature), and long density effects (i.e., CMP checks, flare checks, RTA checks). But checks for DP require long range feature-type effects that permit the identification of coloring conflicts that can be caused, for example, by abutting two independently compliant pieces of IP.

Consequently, becoming DP ready requires adoption of new, highly targeted DP verification tools and methodologies that enable the designers to analyze and optimize their products for manufacturing targets. For low volume/high margin products, the emphasis is not in layout area reduction but in reliability whereas for high volume/low margin products the emphasis is in cost and opportunities to reduce the cost of the manufactured parts.

Manufacturing Technology Readiness

There are three types of double patterning that are actively being explored: a “trim” style, in which certain features are added with one exposure and then deleted with another; a “split” style that puts alternating features on different masks, which theoretically doubles  the effective pitch; and a “sidewall assisted”  or spacer-based style, which combines an auxiliary (Mandrel) mask that defines spacer/sidewall structures and a trim mask to define the final shapes. Sidewall assisted DP provides a more controllable technology at the expense of more restrictions in the layout.

Double patterning style

Subject to DP conflicts?

Solvable by cuts?


Expected CD uniformity

Overlay sensitivity




Dipole single exposure






½ of dipole single exposure



Sidewall assisted



½ of dipole single exposure



Trim style double patterning is the preferred mode of operation since its overlay sensitivity is low, the CD uniformity is mainly a product of one critical mask which limits bimodal distributions, and it is free of DP conflicts. However, its ultimate resolution is dependent on the first exposure which means it cannot attain as high a resolution as the other DP strategies.

Split and sidewall assisted processes also have their own benefits and challenges. For example, split style decompositions can eliminate a DP conflict by splitting continuous structures onto two masks. But because all critical features are defined by two critical masks, each mask has its own CD uniformity and those can differ from one another. Furthermore, there is no guarantee that the CD uniformity maps spatially, which exacerbates image stitching problems.

On the other hand, sidewall assisted double patterning is not as sensitive to overlay and image stitching since there are no “cuts” to resolve DP conflict, but this also limits the types of structures that can be imaged with this technology.

In the end, successful migration to a new process greatly depends on the manufacturing facility as well as the design style being used. Finding the right approach to achieve optimal cost for a new process is not a trivial task because structures that can be easily manufactured with one technology may be very difficult to resolve in another. This creates a growing need to align process development and design strategies to better exploit the benefits and control the limitations of a given process technology. The complexity of choosing the right DP technique is a good example of the need for increased coordination and integration between design and manufacturing, which ultimately allows the electronic industry to keep lowering the cost of manufacturing electronic products at each process generation.




Andres Torres holds a M.S. in Chemical Engineering from UW-Madison and a PhD degree in Electrical Engineering from the Oregon Graduate Institute. He has been investigating the interactions between manufacturing process and electronic design flows to exploit areas of design and process co-optimization that provide more predictable and manufacturable designs. He has published over fifty papers and holds five patents in the area of semiconductor manufacturing. He is currently the Product Lead Engineer of the Litho Friendly Design group in the Mentor Graphics Design to Silicon Division. He can be reached at

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