To be totally honest with you, in the back of my mind, I was vaguely anticipating being crushingly disappointed before I even opened this book. This was due to the fact that, over the years, I’ve been exposed to (and obliged to read) numerous books authored by engineers that feature mind-numbingly turgid explanations coupled with half-hearted attempts at illustration (not that I’m bitter, you understand [grin]). Thus, you can only imagine my delight in discovering that Michael Fingeroff is an excellent writer. He has the rare skill of being able to convey extremely complex information in such a way that readers can understand what’s going on without having their brains leak out of their ears.
One thing you might be wondering is the meaning behind the “Blue Book” portion of this tome’s title. Well, this term is often used to refer to an almanac or other compilation of information. The term “Blue Book” dates back to the 15th century, when large blue-velvet-covered books were used for record keeping by the Parliament of the United Kingdom. But we digress...
First, let’s set the scene and ensure that we’re all tap-dancing to the same drumbeat. Modern chip designs commence by capturing the required functionality of the design at a high level of abstraction. Initially, this representation is used to validate and fine-tune the desired behavior of the design. The next step is to select the design’s optimal architecture and then progress this architecture into an actual implementation. Until recently, the transition from the original high-level representation to the architecture and implementation was performed by hand, which was time consuming and prone to error. Due to tight development schedules, designers rarely had the luxury of experimenting with alternative architecture and implementation scenarios. Instead, it was common to opt for an architecture and implementation that were guaranteed to work—even if the results were less than optimal in terms of power consumption, performance, silicon area, etc.
High-level synthesis (HLS) refers to the ability to take a (typically much-edited) version of the original high-level representation and automatically synthesize it into an equivalent register-transfer-level (RTL) implementation. The human-induced errors associated with a manual translation are thereby eliminated. The use of HLS also allows system architects and designers to experiment with a variety of alternative implementation scenarios. As a result, they can select the optimal implementation for a particular application. Furthermore, HLS allows the same original representation to be re-targeted to different implementations for different deployments.
A number of HLS solutions are available including Catapult C from Mentor Graphics, Synphony HLS from Synopsys, and Bluespec. Because Michael is a technical marketing engineer for the Catapult C product line at Mentor, it perhaps isn’t surprising that his book focuses on HLS in the context of capturing design intent using C / C++ and progressing this high-level representation to an RTL implementation using Catapult C. On the other hand, it might have been useful to the reader if Michael had at least acknowledged the existence of alternative approaches (this is a “Blue Book,” after all).
This minor niggle aside, the High-Level Synthesis Blue Book is extremely clear and well written. It includes useful hints and tips and coding guidelines. The chapter on bit-accurate data types was extremely interesting to me as was the chapter that explained the fundamentals of high-level synthesis. But it’s not fair to single out only these chapters, because the discussions on memory architectures and the scheduling of I/Os and memories are also worthy of note. So are the chapters on combinatorial and sequential hardware, advanced hierarchical design, digital filters...and the list goes on.
The bottom line is that I strongly recommend this book for anyone who is considering the use of an HLS flow including system/algorithm designers, RTL designers, and engineering managers (bless their little cotton socks). The book is of interest to anyone involved in chip design. If you’ve already opted for Mentor’s Catapult C, it will be particularly advantageous—given that it focuses on Mentor’s perspective of HLS.
One minor puzzling point is where one should go to purchase this little scamp. The online price for the hardcover edition from Barnes and Noble is $103.19 (the list price is $128.99) while the e-book edition is a hefty $95.99. The situation isn’t much better on Amazon.com, where the hardcover edition is offered for $107.01. For some reason, it’s not obvious that there’s also a paperback edition available from Amazon (ISBN-13: 978-1450097239). This version, which I have on my desk, retails on Amazon for a much more affordable $15.99. Sad to relate, however, the paperback edition is currently marked as “Out of Print – Limited Availability,” which really isn’t as helpful as one might hope. A Japanese paperback edition is currently in stock, but this would—of course—require a certain level of proficiency with regard to reading Japanese. But don’t despair, all is not lost. Amazon’s Kindle edition is only $8.99. Plus, Amazon offers free Kindle Readers for a variety of devices including PCs and MACs. Personally, for $8.99, I would say that this book is an absolute bargain and that reading it will be time well spent.
Clive “Max” Maxfield is a well-known engineer and freelance writer. Max has authored a number of books on electronics and computing including Bebop to the Boolean Boogie (An Unconventional Guide to Electronics) and How Computers Do Math. Max may be contacted at max@CliveMaxfield.com.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
Congress Center Düsseldorf October 20-21 2014
Seattle, Washington October 21-23, 2014
Irvine, CA October 22-23, 2014
Scottsdale, AZ November 5-7, 2014
San Francisco, CA December 13-17, 2014
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015