Leakage Power and Variability Reduction in a Mobile Baseband Processor

An engineering team at Qualcomm describe how they used the Blaze MO optimization software from Blaze DFM to significantly reduce leakage power and improve parametric yield.

Sorin Dobre, Ke Cao, Charlie Matar, Matt Severson, Omer Sheikh

Controlling leakage power has become one of the most critical design challenges in sub-100nm processes. For mobile applications, designers work within a very tight leakage power specification in order to meet product battery life and package cost objectives. In this article, we describe our approach to reducing leakage power through fine-grained control of transistor gate lengths using Blaze MO™ optimization software, a new tool from Blaze DFM, Inc. A Qualcomm mobile baseband processor was optimized for leakage using Blaze MO and implemented in silicon on a triple-Vt, 90nm low-leakage foundry process. The measured silicon data shows the Blaze-optimized design to have significant leakage reduction and parametric yield improvement compared with the original design.

Leakage Power and Parametric Yield
As a fabless company, Qualcomm designs its chips with an aggressive yield objective across the voltage and temperature process window. For a given die to be sold, it is not enough for it to pass functional tests, it must also meet parametric objectives that include meeting power and performance specifications.

Performance improvements at each successive technology node come at the cost of thinner and leakier gate oxides, and lower threshold voltages that are much more vulnerable to process variation. As a result, as the semiconductor industry moves into production use of 90nm and 65nm processes, leakage power and variability pose serious challenges to meeting parametric yield targets. This threatens to unacceptably increase the time-to-volume ramp of new products designed for these nodes.

The move to 90nm has proven to be difficult for new, high-performance products. Current 90nm products have experienced 12-month ramp times, and ramp times for 65nm process are not likely to be shorter. Any "design for manufacturability" (DFM) approach that can reduce average leakage power and leakage variability will allow us to accelerate yield learning. This is extremely valuable for reducing time to volume production and time to mature yield.

The Qualcomm-Blaze Project
Qualcomm evaluated the potential that Blaze MO offers for shortening our product yield ramp by reducing leakage power and tightening leakage variability. Blaze MO performs a comprehensive power and timing optimization of a finished design prior to the handoff to manufacturing. Blaze MO makes fine-grained adjustments to the target critical dimension for gate length on a transistor-by-transistor basis and communicates these revised targets to the production OPC flow through annotations in the GDSII file transmitted to the foundry.

Blaze MO typically reduces leakage by 10% to 40%. This leakage reduction comes from selectively increasing gate-lengths along non-critical paths. The gate-length biasing gives fine-grain control over the delay-leakage tradeoff of a given transistor; increasing gate length reduces leakage at the cost of transistor speed, while reducing gate length makes the transistor faster at the cost of increased leakage. In leakage reduction mode, there is no change to the overall timing performance of the device, even though leakage is significantly reduced. In timing improvement mode, the performance of the device is improved without any additional leakage.

Blaze MO also reduces leakage variability by 25% to 40%. This variability reduction comes from two sources. First, due to the exponential nature of gate-length/I(off) tradeoff, increased gate length reduces leakage variability. Second, Vt variability is inversely proportional to the square root of device area, i.e., increasing gate length reduces Vt variability, resulting in a decrease in leakage variability.

For the validation of Blaze MO, Qualcomm chose to optimize a baseband processor, which is the "brain of the phone", integrating DSP's, embedded processor and controllers, and additional cores such as video and graphics cores (see Figure 1). Qualcomm must meet an extremely competitive spec for any device that it provides for cellular phones. Power consumption is extremely critical, and power specifications are very tight. Functionality, talk time, and standby time are strictly budgeted, and the chip cannot exceed the budget. For a baseband processor, leakage power is a concern not only in standby modes, but in active modes, as well. When the phone is in active mode, many devices are leaking and circuit-architectural design techniques (such as footer switches) are of no help. Only multi-Vt and gate-length modulation techniques can help reduce leakage during talk time.

Our validation approach was to fabricate silicon using an "A-B" reticle. With the A-B reticle, we fabricated Blaze-optimized die side-by-side on the same wafer with our existing design. This approach allowed us to make direct measurements of the impact of Blaze software on leakage power, performance, and yield on our baseband processor device.

Figure 1
Figure 1: The baseband processor SOC occupies approximately 50 mm2 of die area, and contains nine major macro blocks and approximately 550K standard-cell instances at the top level. Major blocks include an ARM9 core, multiple DSP cores, and video and graphics processing cores.

Methodology
The use model that we developed for Blaze MO is similar to that of a signoff tool, such as DRC or timing signoff. In a bottom-up, hierarchical methodology, we use Blaze MO to optimize the manufacturing handoff as each block is closed. When the top level of the chip is closed, Blaze MO then optimizes at that level. This bottom-up, block-based methodology ensures that the design has been fully optimized at each level of the chip. We found that there was minimal overhead in integrating Blaze MO into the Qualcomm design flow. The tool uses standard formats for all the input and output files – OpenAccess database, LEF, DEF, TCL, SPEF, SDC, Liberty, GDSII and BSIM4. The leakage optimization is performance-driven, i.e., the timing constraints of the original design or block are actively applied during optimization. The leakage-optimized design or block thus honors all of the design's performance constraints. Qualcomm's standard timing and noise signoff flow confirmed that there were no timing violations.

Blaze MO evaluates the effects of different gate lengths on device power and performance using a pre-characterized library of cell variants. These cell variants have slightly different transistor gate lengths than nominal and are characterized using the normal library characterization flow. Note that the layout of the cells does not change and there is no need to create new library cell layouts. The actual biasing of transistor gate lengths happens later – during OPC. Blaze MO automatically generates appropriate annotation layers within the library cell variants to communicate gate bias requirements to the OPC tool. The selection of the cell variants is performed with respect to the process window, design rules and SPICE models, validated by the foundry. Blaze MO automatically identifies cell variants that lead to maximum leakage optimization within a given library size or cell characterization budget.

Blaze MO provides a fine-grain method of optimization that is additive with respect to existing leakage power reduction techniques. The previously existing design flow exploits coarse-grained optimization using the availability of three Vt levels as well as different gate drive strengths. The Blaze MO optimizer can find slack that is left over by the existing "coarse" optimizations, and can flexibly convert timing slack to leakage power savings. A good way of viewing the Blaze CD biasing optimization is that it is a very sophisticated way of moving along the "I(on) versus I(off) curve" on a per-transistor basis, leading to a better overall solution for "I(ddq) versus F(max)" (see Figure 2). By literally performing transistor-by-transistor tuning along the I(on) versus I(off) curve, Blaze can achieve results that are not possible through globally biasing all gate lengths by the same amount.

Figure 2
Figure 2: Blaze MO biasing can produce a solution with better leakage vs. frequency characteristics than can be achieved by process adjustments alone.

Results
Silicon measurements from 4 wafers containing several thousand total die confirmed significant benefits of the Blaze optimization. At the 1.2v/25c (voltage/temperature) corner, the average leakage was reduced by 20%, the leakage variability by 28% and sort yield improved by 20 points at the given I(ddq) and F(max) sort criteria due to improvements in parametric yield. The Blaze optimization did not harm functional yield.

Figure 3
Figure 3: Silicon results: percentage of die meeting spec as IDDQ is swept.

Figure 3 shows normalized parametric yield improvement after Blaze optimization as I(ddq) is swept. The vertical dotted line represents the actual threshold off-current of the I(ddq) test, again normalized to arbitrary units. The pass criteria also included other I(ddq) threshold criteria at 1.2v/25c and 1.35v/25c, as well as all F(max) tests.

The prospects for CD biasing as a technique for leakage and variability reduction are strong at 90nm and remain strong going into the 65nm and 45nm technology nodes. At 65nm, a qualified CD biasing range of 6nm has been established by most of Qualcomm's foundry partners. Coupled with the steeper L(gate) versus I(off) curve in 65nm technology, we expect much stronger results than at the 90nm node.

Foundry Enablement
We are grateful for the foundry enablement and support for the project that were provided by Chartered Semiconductor Manufacturing and the Common Platform Alliance (Chartered, IBM and Samsung). This enablement and support included a pre-qualified CD biasing window, modifications to OPC scripts and DRC/LVS decks (to recognize the Blaze GDSII annotation layers), and all mask and wafer processing, measurement and test.

Conclusions*
Blaze MO unobtrusively integrates into the design flow and provides significant benefits. We have confirmed with a product chip that we can achieve 20% reduction of full-chip leakage and 30% variability reduction using Blaze MO software. We believe that Blaze can be in the toolkit of the yield ramp team. The tool has significant value as a solution to process variation. Additional accomplishments of the Qualcomm-Blaze project include the successful definition of a tapeout flow for the Blaze methodology, as well as definition of the Blaze MO design kit.

*Disclaimer: "While Qualcomm was able to achieve the stated improvements using Blaze MO software on specific chips, use of the software may produce different levels (higher or lower) of improvement for different chips and different process nodes."
Sorin Dobre has spent the past two years focusing on low-power design and new electrical DFM solutions for ultra low-power design optimization at Qualcomm. Prior to that, he was responsible for various design and CAD activities including backend design verification, mask data preparation, IP development, and DFM design methodology at Qualcomm. Prior to that, he was responsible for CAD and DFM development with Metaflow, a fabless CPU design house. He has worked as a researcher in the National Institute for Microtechnology in Bucharest, Romania. Sobre received an MSEE from the University "Politechnica" Bucharest.

Ke Cao is currently responsible for DFM methodology and development at Qualcomm. In his prior position, he was a circuit design engineer at Integrated Device Technology. He received an MSEE degree from University of Minnesota.

Charlie Matar is a director of engineering responsible for SOC design at Qualcomm. He joined Qualcomm as a CPU designer working on ARM-based processors. Prior to that, he worked on microprocessor design at various companies. Matar initially worked at Motorola SPS in microprocessor circuit design and process technology. He received an MSEE in 1990.

Matt Severson is the low-power lead for 7th generation MSMs and contributing architect for many advanced power reduction strategies at Qualcomm. He is the author of several patents. Severson graduated Magna Cum Laude with an MSEE degree from Brigham Young University.

Omer Sheikh is an ASIC designer at Qualcomm CDMA Technologies. He has worked as a design engineer in the communications industry since receiving his BSEE from UC Berkeley.

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