Published on February 21st, 2011

A Future of Collaborative Chip Design

Advances in EDA technology revolutionized the way ICs were developed in the 80s. By separating "what an IC does" from its physical layout, developers were able to focus on each task separately. This changed not only engineering, but also the business of chip development, as many companies took advantage of the opportunity to concentrate their engineering work on the product features that added the most value in the market, and let an ASIC partner handle the physical design and manufacturing.

This division of work along ASIC toolset lines was convenient for its time, but today's semiconductor companies require greater efficiency. Look outside the semiconductor industry and you will see many companies in today's global economy developing their complex systems in a new way, with design visionary companies partnered with subsystem experts and uniquely skilled system integrators. Whether we are talking about iPads or airplanes or TVs, the model is the same.

In this new model, companies look to flexible design partners to collaborate on getting the product roadmap built. Just as the semiconductor industry trend toward foundry-based manufacturing was called fab-lite, this trend toward collaborative engineering can be called design-lite.

Once the trend is clear, the next step is to decide what part of chip design adds the most value, and enables strong profit margins. That becomes the core engineering focus for a product company, and the rest can be shared with an engineering partner to complete.

But which characteristics, you ask? Open-Silicon has been discussing this with industry leaders for the greater part of a year now, and patterns have become clear. Not all markets are the same, of course, nor are development methodologies and organizations created equal. Yet there seems to be widespread agreement that most of physical design can be handled with satisfactory facility by dedicated physical design shops who are seeing many advanced designs per year.

Stepping back a level, most also agree that manually adding in their own IO ring, or integrating standard interfaces, or verifying their AXI bus exhaustively, or negotiating their own PLL IP licensing agreement won't double product margins. Important, yes, but if your engineering partner does 10 PCI Express integrations a year, and can do yours, why not use your own team to work on something that would differentiate and add more value?

Some splits are possible along other lines too. Derivatives are at one end of the spectrum, where the handoff is last year's design along with the vision for how to update that design for today's market. Maybe DDR2 is now DDR3, USB2.0 is now USB3.0, and the new design moves down the technology curve to shed power and cost. And maybe there are potential customers who are out there saying they will use the chip if it only had a new feature. Instead of creating a completely new chip, the product company can design the new feature as an internal IP core and send it, along with the old chip, to their partner for productization. Other categories include respins for bug fixes, software drivers, and evaluation board design.

Furthermore, like all "subsystem experts" these engineering partners will have their own areas of focus. Open-Silicon, for example, has a specialization in making processors run fast. If having faster processors enables a market niche, or expands the target market for a derivative, so much the better.

The market potential of expanding a company's product development capability is tremendous. While the collaboration may look different from program to program, and over time, the results are significant and will drive new thinking into the product planning process. When a company has breakthrough technology they need to maximize their return on investment. Pick the key products to develop in-house, leverage a partner for a few more, and carve out some of the internal team to make the next breakthrough. It is a better model.

Colin Baldwin is Open-Silicon's Director of Marketing and Business Development. He has 15 years of ASIC design and sales experience with Texas Instruments, Arrow Electronics, and Open-Silicon. Currently he is focused on marketing and business development activities for Open-Silicon. Mr. Baldwin received both BEE and MSEE degrees from Georgia Tech.



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