Published in issue of Chip Design Magazine

Prototype Power Issues In Decline?

A three year trend highlights the steady decline of power problems as a cause for ASIC-ASSP respins.

At first glance, the data (see Figure) on ASIC respins from the viewpoint of FPGA-based chip prototypers is boringly predictable. As in years past, designers listLogical or Functional errors the leading cause of chip respins. These errors have been the chief culprits for respins since the early days for chip design.

Figure: Three year trends on ASIC respin data collected from surveys of FPGA-based ASIC prototyping designers. (Courtesy of Chip Design Trends (CDT))

What is a bit more interesting from this data was the citing by prototypers of Specification Changes as a year-over-year growing concern for respins. Signal Integrity concerns are also on the rise, perhaps a result of shrinking process geometrics and the increase in RF and wireless functionality.

The most intriguing result of these trends is the steady decline over the last three years of Power as a respin concern. Some may argue that Power issues may have been listed under the category of Timing and Performance, except this area has also been under decline.

What would lead to power issues no longer appearing as a significant cause of respins? If we apply Occam’s Razor, then the simplest explanation for the decline of power as a cause for ASIC respins is that designers are paying more attention to the power issues than in the past. Low-power design issues have certainly been and will continue to be on the forefront of challenges facing chip, package and board designers in the age of consumer electronics. But for now that particular beast may be tamed – at least for prototypers.

A less simplified explanation might be that power issues are appearing in another guise, which might explain the continued prominence of specification changes, signal integrity and analog performance as causes for respins. Changing specification for power budgets – especially during the later stages of a design – can easily lead to design errors. Signal integrity issues can arise from more clocks running at faster speeds and consuming more power. Analog performance is less easily tied to power issues unless it deals with the integration of power conversion and regulation which is increasing being incorporated into System-on-Chip (SoC) designs.

Whatever the cause, an increased awareness of power is welcome as power continues to be a multifaceted constraint spanning all levels of electronic design. It remains to be seen how long this trend will continue.

John Blyler is the Editorial Director of Extension Media, which publishes Chip Design and Embedded Intel magazine, plus over 36 EECatalog Resource Catalogs in vertical market areas.


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