Published in issue of Chip Design Magazine

EDA Tools for 3D IC Design

Simple Migration of 2D Tools or New Paradigm?

With development costs heading towards $ 100 million for the 32nm process node and below, monolithic mixed-signal systems-on-chip (SoCs) are becoming increasingly costly and time-consuming to develop. Design teams are looking for alternatives to speed time to market and lower costs, and some are finding that 3D ICs with through-silicon vias (TSVs) represent the most practical way – or perhaps the only way – to further increase design complexity and speed.

In applications such as computing, graphics, networking, and mobile consumer devices, 3D ICs promise to meet market demands for miniaturization and higher speeds and bandwidths, as well as lower latency and power. IDMs and large fabless companies are already developing 3D ICs. However, 3DICs will need strong commercial EDA tool support and new ecosystem business models in order to become cost-effective and enter the IC design mainstream.

The traditional EDA point tool approach will no longer be able to meet the cost and time constraints that design teams face. Thus, rather than a point tool approach, a unified methodology across analog, digital, packaging, and pc-board domains is a must.

The good news is that 3D ICs do not require a brand new toolset. By adding “3D aware” capabilities, many existing tools for floorplanning, place and route, extraction, analysis and IC/package co-design can be extended to implement and verify 3D ICs. At a higher level, however, far more than a simple tool migration will take place. The term “IC” in 3D IC is really a misnomer – the 3D IC stacks of tomorrow will be systems, not chips. These systems will integrate digital, analog and RF, logic, memory functions and perhaps even micro-electrical mechanical systems (MEMS). Many will have multi-core or “many core” processor architectures, and will also require sophisticated software development and debug tools.

Designers of 3D ICs will thus really be systems designers, and they will partition complex systems into hardware and software, and then into 3D die stacks. To take full advantage of a key promise of 3D ICs – a shorter and faster path to memory – software must be developed concurrently with the hardware architecture. This transition to a system-level perspective is a paradigm shift, and it will call for a new generation of system and IP exploration tools, hardware and software partitioning capabilities, and of course training opportunities.

Finally, 3D IC design tools at all levels must be firmly rooted in a well-defined, standards-based ecosystem that includes foundries, IP providers, outsourced assembly and test (OSAT) providers, packaging houses, and semiconductor companies. For example, foundries need to provide more than the traditional 2D design rules and process design kits (PDKs) that EDA tools can use. Standards are essential so that everyone can agree on what data will be provided to whom in what formats, and avoid duplicate efforts at manufacturers and/or tool vendors.

The question is not whether or not 3D ICs will be designed and built. The question is whether they will have the EDA tool and infrastructure support that will make them cost-effective outside the walls of a handful of large semiconductor companies. The time to develop that support is now. This article takes a closer look at what needs to be done.

Since multiple-die packages have been around for a number of years, it’s important to clarify what is meant by “3D IC.” Technologies such as wire-bonded system -inpackage (SiP) and multi-chip module (MCM) have been used since the 1990s to refer to packages in which multiple die are mounted on a common substrate. With packageon- package (PoP), one part may be mounted on another part.

Wire bonding limits SiP performance, takes up space, and consumes significant power. A silicon interposer layer can provide much finer, and many more, die-to-die interconnections. A silicon interposer may also include TSVs to provide connections between die on both sides, or between upper metal layers and additional backside metal layers. The use of a silicon interposer with side-by-side die is often referred to as “2.5D” stacking.

This article assumes that a “3D IC” includes two or more stacked die that are directly connected using TSVs. Figure 1 shows a fairly simple scenario in which the bottom die contains TSVs, and is attached to the substrate using flipchip technology. TSVs and micro-bumps provide a path to the second die. More complex 3D ICs could have multiple stacks and layers (tiers) of die, and could potentially have a silicon interposer layer.

Stacked die configurations are already used for large memories today. However, the real value of 3D ICs will be realized when heterogeneous die are packaged together – for instance, logic plus memory, or analog/RF plus MEMS.

Figure 1: A simple 3D IC with two die

3D ICs offer many potential advantages compared to conventional, 2D SoCs. Some of the key advantages are as follows:

  • Reduced mixed-signal challenges
    • 3D die stacks can leave analog and RF circuitry at a mature process node, such as 90nm or 130nm, where proven IP is available and manufacturing challenges are reduced.
    • Sensitive analog circuitry and noisy digital circuitry can now be kept separate.
  • Increased performance, lower power
    • Shorter interconnect delays allow faster interconnect speeds and wider busses between logic and memory, helping meet bandwidth requirements.
    • Power and latency are reduced because big I/Os are no longer needed.
  • Miniaturization, making 3D ICs appealing for compact mobile devices.
  • Proven die-level IP can be used, taking the concept of “IP reuse” to an entirely new level.

Figure 2 shows a comparison of several different implementation choices, including 3D stacks with TSVs on the far right.

Figure 2: 3D ICs with TSVs offer the best performance, power, and density characteristics.

While 3D ICs have many advantages over other implementations, their benefits come at a price. 3D ICs will require extensive modeling and a broader range of design tools. Requirements start with die-level models, block- and gate-level libraries, electrical and mechanical design rules, and multiple sets of physical characteristics, possibly in the form of process design kits (PDKs) provided by foundries and OSATs. Figure 3 gives examples for design kit contents on the left, and identifies three major 3D design steps : system-level design and partitioning, 3D-aware implementation, and extraction and verification for hand-off. The data going into and out of the design tools must be based on industry-standard formats to maximize designer productivity while minimizing risk and surprises.

Design tool support requires far more than point tool enhancements. In addition to tools for hardware and software trade-offs, it requires a unified methodology that considers mechanical, electrical, thermal, magnetic and other effects and cuts across traditional design “domains” such as analog, digital, packaging, and PCB. For example, it should be possible to maintain a consistent representation of design intent across these domains, use abstraction to represent only the data that’s needed at any given step, and converge on the best possible and most cost-effective solution from a system level perspective.

Figure 3: Models and libraries drive 3D IC design flow

This focus on design intent, abstraction, and convergence is called Silicon Realization, and is the guiding principle behind a unified 3D IC implementation methodology developed by Cadence Design Systems.

Developing and maintaining what needs to be handed off to 3D IC design teams will require significantly more effort than today’s “2D” PDKs. Let us consider a few examples:

  1. Given that TSV diameters could be 1-30 microns, they are a significant layout feature. They can place mechanical stress on nearby transistors, impacting circuit performance.
  2. Considering that wafers are thinned to a few percent of their original thickness, strain imposed by TCE (thermal expansion coefficient) differences between metal lines and silicon can lead to warpage and needs to be modeled.
  3. The higher packing density of functions in a 3D stack also results in higher power density and requires accurate modeling of on-chip temperatures and thermal conductivity within a stack, and to the substrate, package, board and heat sink.

Just like high-level planning can impact power dissipation significantly, such planning also can result in significant unit cost savings. To this end, 3D IC system-level exploration tools (sometimes called “Pathfinding”) will provide high-level planning and partitioning. This may begin with partitioning system functions into hardware and software. From there, engineers will determine which proven die-level IP to use for various functions, what process technologies to employ (Si, Ge, GaAs, etc.) , which feature size meets technical and cost targets best, how the individual die will be placed and interconnected in the stack, and whether and how a silicon interposer will be used.

Since a poorly-designed package can cost more than the silicon it contains, co-optimizing die and package is essential for 3D ICs. Designers should be able to build a top-level netlist, optimize I/O connections and power supply lines, and create a package layout in conjunction with floorplanning and routing on the individual die, as well as predict and avoid thermal, power, signal integrity and noise problems.

The board design must be considered as well. The PCB designer needs to know where the 3D IC package will be placed, how well it can be cooled and how the interconnects will be routed. IC/PCB co-design can optimize the placement and rotation of components and reduce the number of layers in the board.

When the time comes to implement the silicon die, designers must have some way to bring design intent – such as the stacked die configuration, top-level netlist, and power requirements – into a digital IC implementation toolset. Once this is done, designers will use 3D-aware floorplanning to decide TSV and micro-bump locations, optimize locations for active circuitry, determine how passives on or in the interposer or package impact performance and cost, and assign signals to bump arrays.

After floorplanning and placement, designers will need to route signals to bump arrays. They’ll need a “double sided aware” router that can handle TSV and micro-bump routing while taking into account the top and bottom adjacent die. Routing tools must be able to run signals across multiple die. A connectivity check should make sure that microbumps on adjacent die are properly aligned.

Like 2D ICs, 3D ICs require extraction and signoff analysis for timing, power, and signal integrity. But depending on the floorplan and the stack configuration, 3D ICs may pose additional challenges such as mechanical stress. Further, onchip thermal characteristics as well as temperature gradients within the stack need to be understood. Designers need to verify the impact of large TSVs on the temperature profile of the die and the stack. In addition to electrical noise analysis it may become important to analyze electromagnetic interference (EMI), since multi-die packages bring high-current and sensitive die much closer together than single-die packages.

Extraction tools need to be extended to consider RLC parasitics for TSVs, micro-bumps, and interposer routing. Timing, signal integrity, power, and thermal analysis tools must be made 3D-aware. That means the analysis should run across the entire 3D stack, and that thermal tools, for instance, should display temperature gradients for the complete stack.

Finally, physical verification tools need to include checks for TSV and micro-bump integrity, such as alignment and geometric shape variation between stacked TSVs and microbumps. After final verification the 3D design data base, together with die- and stack-level test programs, must be provided to foundries and OSATs – and the details of what gets handed to whom, and how, still need clarification.

Test raises many challenges for 3D ICs, and solutions will require innovation in design for test (DFT) software, standards, and the test equipment hardware and software itself. Challenges include accessing die inside a stack, creating a known-good die (KGD) stack, and avoiding damage by wafer probes to thinned wafers. DFT tools for scan insertion and built-in self test (BIST) need to provide 3D controllability and observability. The emerging iJTAG (IEEE 1687) standard may make it easier to embed test structures in die for 3D stacks.

3D ICs let design teams implement entire systems costeffectively in ONE package. For the most part, existing IC implementation and analysis tools can be extended to comprehend a third dimension, and allow 3D designers to rely on familiar and proven tools. Equally important is the availability of accurate and complete manufacturing data and material characteristics provided to system and chip designers by foundries, substrate, and packaging providers as well as OSATs. Ecosystem partners that work in relative isolation on 2D ICs today will need to communicate and cooperate much more closely to design and manufacture cost-effective 3D ICs. Exchange formats, interoperability standards, clarification of hand-off responsibilities, and even new business models may prove useful and will allow our industry to fully benefit from utilizing the 3rd dimension for circuit and system design.

Beyond tool migration, a paradigm shift is taking place. Part of that shift involves breaking down the real or psychological “walls” between analog, digital, packaging, and PCB domains, and developing an application-specific, unified 3D IC design solution that provides co-design and co-optimization across those domains. Another part of the shift stems from the realization that 3D ICs will become “systems,” and that designers will need to do high-level planning and partitioning and embrace both hardware and software domains to find the best 3D solutions. Silicon IP will go beyond RTL code and hard macros and become reusable, proven hardware in die form. 3D ICs will ultimately redefine “chip” design and take it to a higher level – both literally and figuratively.

Herb Reiter founded eda2asic Consulting in the spring of 2002 to increase cooperation between EDA suppliers and semiconductor vendors. In this role Herb introduced many EDA tools, flows and methodologies to reduce IC design time for the semiconductor vendors and to lower power dissipation and unit cost for their products. Previously Herb worked for 5 years in business development roles at Barcelona Design, Synopsys and Viewlogic. The PrimeTime sign-off wave and the TSMC reference flow # 1 are highlights of Herb's accomplishments at Synopsys. From 1980 to 1997 Herb worked in both business and technical roles at VLSI Technology and National Semiconductor to market ASICs and ASSPs. Herb earned an MBA at San Jose State University and Master Degrees in Business and in Electrical Engineering at the University and at the Technical College in Linz/Austria, respectively.

Samta Bansal leads 3DIC efforts and also serves as the Sr. Product Manager for Encounter Digital IC implementation at Cadence Design Systems, Inc. She has more than 12 years of experience working with semiconductor leaders including both 2D and 3D-IC design space. Prior to Cadence, Samta worked at Synopsys looking into the front end technologies. With hands on experience on front end for 8 years and moving to Back end, Samta has a very good understanding of the evolution and challenges the industry has been going in terms of design requirements and is very passionate in driving this shift of the industry from 2D to 3D-IC within Cadence and working with the ecosystem partners. Samta has Masters in Physics, Bachelors in EEE from BITS, Pilani and MBA from Santa Clara University.


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