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Published on June 07th, 2011
This year’s IEEE Daniel E. Noble Award will go to Dr. Mark L. Burgener and Ronald E. Reedy, co-founders of Peregrine Semiconductor. They will be honored for “basic research and development of silicon on sapphire technology culminating in high-yield, commercially viable integrated circuits.” The Noble award is presented annually to those individuals who made a significant contribution to emerging technologies. Low-Power Engineering talked with Peregrine’s founder, Ron Reedy, and Chief Marketing Officer, Rodd Novak, about the struggles to bring SoS technology to the commercial world. Here is a portion of that interview.
LPE: Making silicon on sapphire (SoS) a commercially viable process must have been full of challenges, from tool flows and manufacturability.
Reedy: We spent the first 10 years developing the process at multiple, different fabrication facilities (fabs). Surprisingly, there is a huge amount of effort that follows after the fab work, for example, learning to singulate sapphire. Since sapphire is a very hard material, it was difficult to singulate or dice up the wafers into chips. Other equally important questions arose, such as SoS packaging. Testing was also an issue, since sapphire’s transparency does not work well with standard automatic optical inspection equipment.
We faced fewer challenges in the design tool flow area, since we used all of the standard industry tools. Further, all the processes were industry standard, but we did have to tweak the receipts to hone them for high-yielding production. Simple production is not enough. If you cannot yield it, you are not there. That is the very time consuming and expensive part.
We can make 10 million chips per week. I’m guessing that no more than 10 million or 20 million silicon on sapphire chips had ever been shipped prior to our company entering the picture. We are doing in a week, what the whole industry struggled to do in a lifetime. Equally important, we are achieving yields that the market can afford to pay for the required device performance. Price is important, because you can price yourself out of the high performance analog market.
LPE: Is your process easily transferrable between different foundries?
Novak: Yes. We use all standard processing equipment. Our SoS wafers run down a CMOS line without any impairment to their fab. Further, we have ported it to three fabs; Rohm (formerly Oki Semiconductor), MagnaChip Semiconductor, and UMC. In the last 10 months, we announced work with IBM. So the technology is very transferrable. Perhaps a more important point is that we can transfer products between fabs, which is something very unique for RF front-end devices. In alternative technologies like Gallium Arsenide (GaAs), the fabs are so highly tuned in that it is nearly impossible to transfer a product from multiple fabs with the same performance level. Conversely, we are able to supply the market from multiple fabs, providing CMOS scaling as well as redundancy to the front end. Prior to that I think you’d find customers very wary of single sourcing an RF front end but not so wary of single sourcing a transceiver or a baseband. We are bringing that CMOS mentality up to the front-end.
LPE: The recent tsunami in Japan has taught the technology world that single sourcing can be risky.
Reedy: We are still dissecting the impact on the supply chain of the disruptions in Japan. Few vendors can see all the way down their supply chain. Everybody is holding their breath, worried that the natural disaster might have damaged a little known company that supplies a crucial chemical additive for 80 percent of the world supply of something. Diversity in the supply chain is important. People are rethinking the whole just-in-time manufacturing mentality because it is so highly tuned but not very robust. Most of the world’s products are going through a specific fab with a specific process. That can be risky.
LPE: How does silicon on sapphire work?
Reedy: In a typical CMOS process the transistors are either deposited on or ion implanted into photographically defined areas. When you build up all the layers it turns into the magic of an integrated circuit. But underneath all of that, 99.9 percent of the thickness of that chip is a solid slice of silicon, which is a semiconductor. Partial conducting things tend to behave in strange ways. You can turn them into transistors, but you can also turn them into current leakage paths.
In essence, our SoS process slides out all of the silicon substrate and slides in a nature’s best inert dielectric insulating material called sapphire. That’s not how you do it, but that is the end result. The beauty is that sapphire is a perfect substrate for RF performance. Layered up from there is a pure CMOS structure. No extra metal layer masks are involved, although we did have to tweak the typical CMOS process recipe to change how much energy we use in an ion implanter. If you implant too deep, the IC structure lands in sapphire and does nothing. Aside from a few tweaks, our process uses the same design tools, tape out and masks as a regular silicon substrate.
LPE: As an insulating substrate, sapphire has very low parasitic (unwanted) capacitance. Doesn’t this further complement the existing low power benefits of CMOS?
Reedy: CMOS was one of the most idiotic things that anyone had ever dreamed up. It is expensive, complicated, latches up, and requires twice as many steps to make as other material. But it has the magnificent feature of being extremely low power. CMOS was not really used until the IBM 386 started catching fire in the PCs. Then someone suddenly discovered power dissipation was a problem and CMOS became popular. CMOS on Sapphire turns out yet lower power while maintaining incredibly high performance. The problem with silicon on sapphire was that no one could produce it.
LPE: Let’s talk about production numbers for SoS devices.
Novak: We have shipped over 700 million devices to date, driven mainly by the handset market. Other important segments include space satellites, military-aerospace, test equipment, displays, and broadband markets. We have well over 1,000 customers right now in very unique markets.
The satellite market was about the only real success for silicon on sapphire technology, prior to our company entering the market. SoS was radiation tolerant and extremely low power. Space systems like satellites are very sensitive to power consumption. Further, if you can save on power, you also save on cooling. We continue to support that primary market in the K-U bands and below.
LPE: You’ve been able to achieve high production numbers. Is volume really that critical in the niche market of RF and microwave systems?
Reedy: I’m a big admirer of what the GaAs guys have done, but in the end nothing on this planet is as manufacturable as silicon CMOS. As I’ve often said, soybean farmers cannot make soybeans to the level of reliability that we can make SoS devices. We ship a million chips with the goal of zero returns. For the last three to six trailing months I think we have had two electrical returns out of 100-some million handset devices. There is no way that individual ears of corn are that good. In our business, volume drives innovation, not the other way around. People think that if you innovate something it drives the volume. That is not the case. Only high volume markets can rationalize the expense of these developments, such as liquid crystal displays in TVs.
LPE: Earlier, you mentioned the importance of yield. How does volume relate to yield?
Reedy: You cannot afford to get the yield up if you are not in high volume because it is very expensive to find every last 1% of a yield problem. You don’t get high yield by accident. You get there kicking and screaming the whole way. But if it is a high-volume market, then it pays for itself in that yield. All the other markets then get that same yield. That applies not only cost but reliability. It’s been proven from the very earliest days of the integrated circuit that high yielding wafers are high reliability wafers.
John Blyler is the Editorial Director of Extension Media, which publishes Chip Design and Embedded Intel® Solutions magazine, plus over 36 EECatalog Resource Catalogs in vertical market areas.