Analog Inside: The Evolving Analog Interface for Wireless-Communications Modems

Converging the digital and analog signal-processing domains is necessary to deliver required bit rates.

The need to transfer large amounts of data wirelessly is driving the adoption of new and more powerful wireless-communications standards. To achieve the required high data rates at a low cost and low power dissipation, advanced system-level solutions have been developed in addition to advanced architectures for the analog front end (AFE) and radio-frequency (RF) transceiver. This article reviews the emerging wireless-communications protocols, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), and IEEE 802.11n and 802.11ac. It focuses on the characteristics of the AFE and how it is integrated into the communications modem. The article also discusses how the use of robust dataconverter technology enables the AFE to be integrated with the digital baseband processor in very deep-submicron nodes—while reducing the power budget and overall system cost.

Emerging Wireless-Communications Protocols

Wireless-broadband communications is arguably one of the defining technologies of the modern lifestyle. Its relentless adoption throughout the world has empowered individuals in ways that weren’t expected when the technology was originally deployed. It has changed both users’ personal and public lives. In turn, the hunger for higher data rates forces developers to leverage new broadband connectivity protocols to more efficiently utilize the available frequency spectrum. The dynamics of this market is such that new releases of successful protocols are progressing as the previous generation is still being deployed—be it in the cellular (LTE or LTE-A) or WiFi domain (IEEE 802.11ac or 802.11ad), as shown in Figure 1.


Figure 1: Shown is the evolution of wireless-communications protocols (from 1990 to 2011).

 LTE-A employs the same frequency bands as LTE. Yet it uses carrier aggregation to 100-MHz channel bandwidth and other techniques, such as larger multiple-input multiple-output (MIMO) arrays, to achieve bit rates up to 1 Gb/s. At the same time, it is compatible with legacy LTE transceivers.


Similarly, IEEE 802.11ac uses the same frequency bands as 802.11n. In addition, it uses carrier aggregation (up to 160 MHz) and larger MIMO arrays to achieve the desired higher bit rates. At the same time, it maintains compatibility with IEEE 802.11n.

In contrast, IEEE 802.11ad takes a different approach. It explores the unlicensed 60-GHz band to achieve the required bit rates. In this way, it isn’t compatible with legacy products and will not be further discussed in this article.

All of these protocols use multi-tone orthogonal-frequency-division-multiple-access (OFDMA) modulation techniques. They take advantage of multipath effects to increase the spectral efficiency and {WORD MISSING?} to channel imperfections.

These protocols tend to use deeper quadrature-amplitude-modulation (QAM) constellations (up to 256 QAM) while requiring larger channel bandwidths. For example, typical third-generation (3G) protocols, such as code division multiple access (CDMA), use channel bandwidths up to 10 MHz. Yet the LTE wider channel occupies up to 20 MHz while LTE-A may use a very wide 100-MHz channel (using channel aggregation techniques). In the WiFi arena, IEEE 802.11ac’s maximum channel bandwidth can reach up to 160 MHz, depending on the region.


The Wireless-Communications Modems


Figure 2: This block diagram provides an example of a 2x2 MIMO wireless-communications modem.

The wireless-communications modem system comprises an analog RF block, which translates the over-the-air communication into baseband analog signals (see Figure 2). In addition, a digital baseband processor block translates the modulated signal into meaningful communications content. Between these two blocks, a wireless baseband analog interface converts signals between the analog and digital domains. This wireless analog interface block, which is composed of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), is collectively known as the AFE.

Traditional single-input and single-output (SISO) implementations of the modem required a single transmit and receive path. The AFE supporting these implementations integrated a single IQ-DAC and IQ-ADC in the signal path.

The expansion of the MIMO concept requires the multiplication of parallel transmit and/or receive data-processing paths. They’re merged in the digital baseband processor, leading to an exponential increase in the digital processing power. This approach also adds complexity to the RF and analog interface circuitry, requiring more instances of the IQ-ADC and IQ-DAC to support each path.

To address the increased requirements in terms of digital processing (while improving or at least not degrading the system power dissipation), the digital baseband modem is implemented in deep-submicron processes. The migration to a 28-nm process and beyond is accelerated by the recent trend to integrate the baseband processor with the application processor in a single die. Yet the analog—and in particular, the RF circuitry—cannot easily take advantage of the low-voltage characteristics of the deep-submicron processes. As a result, their cost/benefit sweet spot is in more conservative process nodes, such as 65 nm.

The AFE is the interface between the digital domain and the RF-transceiver domain. The digital domain is very complex and quickly migrating to the 28-nm process. Yet the RF-transceiver domain evolves at a much slower pace. Typically, it also is implemented in a separate die.

Typically, this AFE is integrated with the digital baseband modem. Because it can simultaneously act as a very effective and low-power interface between the digital die and analog RF die, it avoids wasting power with additional, specific interface blocks.

Defining AFE Performance

To process wider channel bandwidth and deeper quadrature amplitude modulation, system sensitivity must be improved. Sensitivity correlates to the system’s signal-to-noise ratio (SNR). In order to achieve this goal, the SNR performance of each component block—including the AFE—also must be improved.

The AFE’s SNR performance is determined by the required receive sensitivity. That sensitivity, in turn, is determined by the modulation scheme and amount of rejection of adjacent signals implemented in the RF and analog baseband processing (see Figure 3). Given today’s modulation schemes and processing gain, SNR in the range of 65 dB is generally required from the ADC.

Figure 3: Shown is a complete analog receive data-processing path including the AFE.

 Another key AFE performance parameter is the sampling rate. It takes into account the spacing between tones and the channel bandwidth in order to simplify signal filtering and avoid additional interference within the band. For LTE and IEEE 802.11n, the maximum sampling rates used in the AFE are typically 61.4 and 80 MSamples/s, respectively. Multiples of these sampling rates can be used to achieve higher oversampling rates, thereby simplifying anti-aliasing filtering and increasing processing gains.

More advanced protocols use carrier aggregation to achieve larger channel bandwidths. But the various channels that are being aggregated don’t need to be continuous or in the same band. Therefore, they can be treated as separate channels, with their information aggregated in the digital baseband processor. Alternatively, aggregation can be achieved within the RF block. In these cases, the dataconverter inside the AFE must have bandwidth that’s proportional to the number of aggregated channels. The sampling rate must then be increased by the same amount.

Supporting any of these modes is demanding in terms of power dissipation, due to the multiplication of signal channels within the circuit. Therefore, the initial use models expect very power-sensitive handheld devices to support the legacy LTE/802.11n protocols. In contrast, the infrastructure and other home-networking devices, which are less power sensitive, will support the advanced, higher-bit-rate modes.

Dispelling The Myths

As mentioned previously, the AFE is commonly implemented inside the digital system-on-a-chip (SoC). This partitioning avoids the addition of high-speed digital interfaces, which is advantageous in terms of total system power dissipation and system costs.

As the digital SoC moves to the 28-nm process, it’s important to evaluate whether the AFE can still be integrated in the SoC and whether system partitioning is still valid. The integration of analog IP (which is capable of processing broadband signals with high resolution) in complex, deep-submicron SoCs is sometimes considered uneconomical and a technical challenge.

Fortunately, reality is brighter than this! Let’s look at the myths and facts that explain how data-conversion technology has kept pace with modem requirements as well as with the process node of choice.

Myth: Analog IP does not scale with process node. It’s too area expensive to include analog IP in a deep- submicron SoC.

Fact: This analysis assumes the use of the same circuit techniques that were utilized in older process generations. Recent developments toward “digitally assisted” analog IP are already showing that it’s possible to reduce the area of the analog blocks. In the case of AFE dataconverters, the use of digital background calibration transfers the circuit complexity from analog to digital. It also makes the dataconverter more immune to the limitations of devices that are available in these processes.

By avoiding the extra analog circuitry that would be needed to achieve the correct performance using traditional analog design techniques, the analog block becomes small. The digital block therefore becomes a significant portion of the total area. This means that significant gains in area can be achieved simply by scaling the digital block as the process node shrinks.

Overall area reduction of as much as 50% can be achieved by these techniques. An additional area reduction up to 25% is possible simply by moving to smaller process nodes.

Myth: The power-dissipation and supply levels used in analog IP are incompatible with deep-submicron SoC availability.

Fact: The previously mentioned “digitally assisted” techniques allow the use of imperfect core devices supplied at low voltages (~1 V) while achieving the required performance. This results in significant power savings. Additionally, the speed of these devices is very high, which allows very high sampling rates to be achieved at moderate current consumption.

In the interface circuitry, higher supply voltages are sometimes used in order to accommodate the signal levels that may be present in legacy RF integrated circuits (RFICs). Even these can be in the range of 1.8 V—a voltage commonly used in any system.

Further techniques—like power-dissipation scaling with sampling rate and fast wake-up and shut-down of the dataconverter—mean that they’re very effective power devices. As a result, they don’t compromise the power budget of the SoC. By avoiding an extra digital-interface block, the total system power consumption becomes even lower.

Myth: The risk of integrating analog IP is too high.

Fact: The design and validation techniques used in today’s dataconverters are excruciatingly detailed and inherently robust to process weaknesses. Tens of thousands of simulations are carried out in order to determine how the circuit behaves in the presence of all process non-idealities. Furthermore, robust design techniques are employed throughout the design (i.e., differential signal processing, isolation of critical sections, power isolation, and routing). They guarantee the robustness of the dataconverter to the harsh environment in which it will operate. With final silicon validation, the block is validated and the risk of integration is therefore minimized.


Wireless-communications modem applications are evolving at a fast pace, due to the introduction of new and more advanced communications protocols. In the communications modem, the digital and analog signal-processing domains converge to deliver the required bit rates. The AFE is a mandatory interface between the two domains. It is commonly integrated with the digital baseband processor.

Data-conversion technology has kept pace with the modem requirements as well as the process node of choice. New design techniques allow the dataconverters to take advantage of the process technology in order to reduce area as well as power dissipation. At the same time, they improve robustness to process non-idealities and the harsh SoC environment.

Manuel  Mota is the technical marketing manager for data converter IP within the Solutions Group at Synopsys. He joined Synopsys from MIPS Technologies, and before that worked as an analog IP designer for Chipidea Microelectronica (Portugal) with responsibility for the design of PLL and Data Conversion IP cores, as well as complete analog front-ends for communications.  Manuel holds a PhD in Electronic Engineering from the Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow.

For more information on Synopsys DesignWare® Data Converter IP solutions, please visit:


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