Published on September 20th, 2011

The Next NoC

Sonics rolls out 1GHz network technology in preparation of future bandwidth requirements.

How fast do signals have to travel inside and outside of an SoC? That question may be more difficult to answer than many questions in the semiconductor world because so far it hasn’t been a problem. 

But that hasn’t stopped companies from looking beyond the current technology needs toward what will be required over the next couple of process nodes. The most recent example of this comes in the network-on-chip world, where Sonics has just boosted the speed of its NoC to 1GHz. 

What makes this particularly compelling is that it provides headroom for chip architects looking to create derivative chips several generations in the future. No chip companies can afford to develop chips at the leading process nodes without planning dozens of derivatives because the NRE costs are so exorbitant that they need to be amortized across dozens of chips. Add to that a move toward Wide I/O in 2.5D packages and the need for leeway in speed of both on-chip and off-chip communication becomes critical. 

“The application processor market tends to be the one where you want five pounds of stuff in a one-pound bag and the battery needs to last twice as long as it does,” said Jack Browne, senior vice president of Sonics. “Those things have the biggest system-level challenges for performance and power. That is the environment in which we worked on this technology. We didn’t look at it as NoC and crossbar. We asked what are the system requirements that our customers need to get the right performance.” 

This kind of headroom is equally interesting in 2.5D and 3D stacks of chips, where bottlenecks need to be addressed even before all the pieces that will be packed in the stack are known. For example, there will be a single power budget for these stacked die, even though some of the pieces may have been created at older process nodes when issues such as power and other physical effects were not a consideration, and they may utilize much slower bus infrastructure and processing speeds than are considered acceptable by today’s standards. As a result, other areas of the design may need to compensate for those older technologies.

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