Published on October 14th, 2011

Integrated Design and Full-Wave Analysis of Mixed-Signal 3D Package Designs


A unified chip/package/module co-design methodology can address a number of analog and digital design integration issues. These challenges include the best placement of die I/O buffers and die bumps for optimal floorplanning; sufficient spacing between the die footprints in a package; and interconnect parasitics that are not so high as to cause signal integrity problems for critical signals.

The IC that functions properly as a standalone may fail to perform when put in a package. This may occur when voltage drops on package power rails, or when the package interconnect causes too much attenuation on the signals moving from one IC to another. RF passive structures made on silicon substrates may function differently in electromagnetic (EM) surroundings due to package planes. In the absence of a unified chip/package/module co-design methodology, the co-design and co-analysis of chip and package is extremely challenging.

While the physical co-design of ICs and packages has been an industry focus for last few years, we now need to extend physical co-design with a more systematic method for co-analysis of the IC and the package. The approach should be capable of analyzing high-frequency signals spanning multiple technology domains (i.e., time and frequency domain as well as from within the chip, through the package, and onto the module/PCB substrate).  Such co-analysis methodologies require thorough power and signal integrity analysis using a full-wave three-dimensional (3D) simulation technology. With RF and analog content, design engineers need to simulate ICs in the context of package parasitics.  The ability to use a repeatable flow throughout the design cycle is a key requirement to meet tightly managed product schedules.

As frequencies increase to handle data at gigabit rates, “rules of thumb” and 2D or 3D quasi-static extraction technology are not sufficiently accurate to meet the design challenge. Quasi-static solvers assume that electric and magnetic fields are independent from each other. These solvers work well when physical structures are smaller than the signal wavelength order; however, when the frequencies are higher, it is important to consider the effects due of time-variant electric and magnetic fields interacting. This mandates that the unified chip/package co-analysis flow be powered by an integrated full-wave solver.

In this article, the authors will describe how productivity can be enhanced by using an integrated flow that combines full-wave solver technology with IC/package design, analysis, and simulation. Such an integrated flow would allow seamlessly combined functional simulations of circuits across both the IC and package, and it would enable accurate modeling of RF and complex 3D structures that may be part of combined geometries across the IC and package.

Unified IC/package design and analysis flow integrated with a full-wave solver

Figure 1 shows the ideal flow that combines full-wave (FW) solver technology with IC/package design, analysis, and simulation flows:

  • IC and package layout flows are driven by a single schematic. This allows simulation of the complete (mixed-signal) system across IC/package with parasitics annotated from FW 3D solver output
  • On-chip/off-chip passive structures are modeled using FW solver technology
  • IC and package layouts are merged to allow FW solver extraction on the combined structure
  • Signal integrity (and power integrity) works with models extracted from the FW solver
  • FW solver is integrated with the layout and schematic environment, making it easy to select design objects and launch solver operations

Figure 1: Ideal integrated flow



Selecting objects in layout for 3D FW extraction

Traditionally, one of the biggest challenges a system-in-package (SiP) designer has to face is to import the layout into a 3D field solver framework and then run extraction to obtain results. This forces the designer to leave the design environment and move to the solver toolset. Any changes in layout need to be re-exported into the solver toolset as a complete database through manual steps. The designer then has to re-select the nets and instances in the solver framework and, at times, apply 3D settings (bond wire specifications, die bumps, and package-ball parameters). Different tool GUIs, commands, and possible database translation issues exacerbate the challenge.

The designer should be able to select nets and instances in the layout itself and then run the solver from within the layout environment (Figure 2 provides a sample GUI showing settings that should be accomplished in the layout environment for FW extraction). The partial database extraction and 3D settings should automatically get passed to the solver. This provides a better handle for the SiP layout designer to make layout changes and run the solver in a repeated and efficient mode. Any discrepancies in settings should get reported as part of the solver’s running process to guide the layout engineer to make corrections for solver’s extraction process.

There could be cases where IC/package structures need to be analyzed as combined structures for a meaningful system simulation, and in such cases we need to use common schematics to select the structures.

Auto-setup required for 3D FW extraction

The process of model extraction for FW solvers is more complex than quasi-static extraction. FW solver users must carry out multiple steps to:

  • Identify reference planes (VDD/VSS) closest to nets/structures to be analyzed
  • Identify locations on traces or shapes for application of ports. These are usually centered on pads that represent pins of the trace
  • Apply ports from pin locations to reference planes through closest paths
  • Lump the ports for port-grouping when the user wants to reduce the number of ports
  • Set differential ports for differential pairs
  • Set boundary conditions
  • Keep minimal stack-up by removing the layers that would contribute little to the accuracy of the model, thus reducing solver runtime

With the integration of the FW solver into the design and analysis flow, each of these steps becomes automated, thus making the designer’s 3D modeling task simple and fast.



Another challenge faced by designers in a traditional SiP design flow is that a model (S-Parameter) extracted by the FW solver has to be manually imported into the signal integrity/power integrity (SI/PI) toolset for running respective analyses. This requires:

  • Creation of a symbol that can be hooked into the SI analysis canvas
  • A way to connect the model ports to the rest of the analysis topology

With an integrated environment, the model should get consumed into SI/PI analysis in an automated manner, either as a black-box symbol bound to the solver-extracted model or through a mapping file that connects the model nodes to the rest of the topology.

 SI analysis

SiP designers usually start with extraction of interconnect from the layout where the topology maps to the series of transmission line elements (representing micro-strips, striplines, and vias). For better accuracy, each of the elements is synthesized into a model by running the 3D FW solver on individual elements.

For further accuracy, it should be possible to replace the entire transmission line topology with an S-Parameter model of the entire structure considered together as a single element. This replacement should be automated to save time. Figure 3 shows an S-Parameter model representing 3D interconnect. If users want to modify the combined 3D structure, then they should be able to launch the 3D solver editor from the S-Parameter symbol to bring the detailed structure up for editing and re-extraction.

Figure 3: Extracted S-Parameter model consumed into the SI environment

PI analysis

PI analysis requires special effort to extract power rails when using a FW solver. Unlike the quasi-static case, we need to extract each power rail (e.g., GND) with respect to the other power plane (e.g., VDD) and vice-versa. This task is typically achieved by extracting the power delivery network (PDN), which consists of power supply, converters (voltage regulators), decoupling capacitors, and interconnection (see Figure 4).

Figure 4: Schematics of a PDN

Since there could be hundreds or thousands of VDD and VSS pins, it is important to have some expertise on how to group the ports by shorting the pin locations followed by appropriate port applications. The automated process can group the ports much easier.

As part of the automated model consumption into PI analysis, we need to generate a pin-map file that maps all model ports to respective die cells to complete the connections of the power-rail model to respective die cells where the power is supposed to be delivered into the IC. This enables chip and package PDNs to be analyzed at the same time. The integrated flow should create a pin-map as a header to the S-Parameter model to show connections of the power-rail model to the board-side VRM and to die-bumps that connect to the die model.


When SiP designs are mixed signal, which is most often the case, the designs will have analog and/or RF content. The portions of the design that have analog/RF need to be analyzed through schematic-level simulations. The accuracy of such simulations depends on the inclusion of accurate parasitic models of interconnects representing layout traces. Also, there are metal passive structures like on-chip/off-chip spiral inductors that have to be accurately modeled for good results.

Traditionally, multiple manual steps have been required to perform parasitic-aware functional simulation. These manual steps include:

  • Create a new schematic that contains the portion of the design that needs to be functionally analyzed (such as the RF/analog portion). This design could run across the package and multiple ICs being used inside the package
  • Create a symbol for the parasitic model extracted from the layout by the FW solver
  • Locate the nets in the schematic and insert the model by instantiating the previously generated symbol
  • Bind instances like inductors (spiral) or capacitors (digitized) to FW models. The instances could be on the package (off chip) or inside the IC (on chip)
  • Simulate the design to evaluate performance

With an integrated environment, all of the above steps will be automated and easily repeated when changes are made in the design.

Schematic-driven object selection across IC/package

Designers use schematics to capture analog/RF-IC and package design. A single schematic-driven environment that holds the design of the entire package and the ICs being used in the design is ideal to support co-design.

As shown in Figure 1, the same schematic should be able to write to respective portions to package layout and IC layout tools. This enables the selection of structures across IC/package by choosing objects in a common schematic (across hierarchies). Such selection of a group of structures (across IC/package) creates a combined structure of IC and package by merging the geometries and stack-up definitions. This can work well for vertically stacked dies on a package and allows handling of critical cases like analysis of on-chip spiral inductors with respect to package power-planes.

A schematic-driven solver flow also allows the opportunity to run a FW solver on passive structures before the layout is done. The parameterized passive structures can be converted to corresponding layout footprints on the fly (based on parameter values) using the stack-up technology to which it is mapped. This conversion can be followed by a solver run for early simulations.

Auto-generation of package parasitic-aware IC testbenches

IC design by itself is complicated. If multiple die(s) in a package are to be simulated together, the problem could become even more complex. Usually, the designer wants to simulate portions of the system to speed up exploration and make design improvements.

The ability to extract portions of the IC and package design to create a derived schematic view for simulations makes it easy for the designer to incrementally improve the design along with corresponding interconnect parasitics. Such a capability allows quick selection of critical components of the IC design to auto-generate a new schematic view with a partial design. The floating nodes of such an extracted design become the interface nodes of the die under test. These nodes have to be connected in the test design with other components before running the simulation.

Any changes made in the derived IC design (being used in the test design) to meet performance goals can be compared to the master IC design for any differences in terms of values and properties. The differences across testbench and master design could be resolved (updated) through a commit process.

Consuming S-Parameter models into IC/package schematic simulation

As the SiP floorplan and trial routes are modified, corresponding parasitics should immediately be reflected in the IC test design to measure the overall performance in a realistic environment. There needs to be an automated way to import package interconnect parasitic into the IC test design to generate package-aware parasitic views of IC/package schematics.

  • The S-Parameter model generated by the FW solver should be inserted into schematic nets automatically
  • It should be possible to automatically bind a model extracted of a layout footprint with schematic instance
  • It should be possible to replace a group of objects (nets and instances) with a solver-extracted model symbol
  • It should be possible to annotate a solver-generated model to multiple instances if the designer believes that the model can safely represent multiple instances. For example, a bond wire profile extracted by a FW solver could be applied to all bond wires in the design that have the same profile (ignoring the coupling effects)

Figure 5: Extracted parasitics consumed into the system schematic


The single schematic-driven IC and package layout/solver flow allows the simulation of mixed-signal systems across IC/package with extracted parasitics. Such a solution would allow a) schematic-driven object selection across IC/package; b) auto-generation of package parasitic-aware IC/package testbenches; c) modeling of on-chip/off-chip structures both in synthesis and analysis mode. The ability to merge IC and package layout structures to allow FW extraction on a combined 3D structure would take different size structures and combined stack-ups.

An automated flow for consuming the extracted model for signal and power integrity is also required in order to automate the process of connecting the model to the IC/package interconnect topology especially when connections go up to 100s of I/Os from the package subcircuit to the IC model subcircuit.

Finally, an integrated FW solver to layout is required. This would allow the designer to make changes in the design and re-analyze without having to leave the design environment and move to the solver toolset.


Brad Griffin is the director of Product Marketing at Cadence Design Systems, Inc. responsible for system-in-package and signal integrity solutions.




Taranjit Kukal is the architect for the Product Engineering group at Cadence Design Systems, Inc. responsible for RF system-in-package, high-speed modeling, and PSpice solutions.




Antonio Ciccomancini Scogna is a Principal Engineer at CST of America Inc. responsible for the analysis of high-speed digital systems including electromagnetic packaging effects, signal integrity, and power integrity.

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