Published on November 07th, 2011
Improving yield is an important bottom-line issue—particularly for high-volume products. Semiconductor companies usually invest in major efforts to maximize yield during the first silicon debug, early-yield ramp-up, and yield ramp-up stages. Less effort is put into improving yield at the mature production stage. If mature yield levels are improved, however, a company’s profit margin and competitive capability greatly increase. For example, say 1,000,000 pieces are produced per month and sold at $6 each. Improving the mature yield by a mere 1% would mean that 10,000 more devices are shipped. This may add to a gross profit of $300,000 a year—assuming the cost of packaging and silicon is about $3.5 per device [($6-$3.5)*10,000*12 = $300,000]. The problem lies with traditional yield-analysis methods, as improving the yield of a mature process is difficult. And the return on investment often cannot be justified—even for high-volume products.
Yield loss during manufacturing can be due to complicated reasons. For corrective action to be taken, the root cause of yield loss therefore needs to be identified. The scan diagnosis method does this by taking advantage of the design-for-test (DFT) structures and automatic-test-pattern-generation (ATPG) patterns—along with the design description and manufacturing-test fail information. Through simulation, scan diagnosis identifies the location and type of defect that’s most likely to be causing failures. With its industry-proven quality in terms of accuracy and resolution, scan diagnosis has long been a staple of physicalfailure- analysis (PFA) labs. More recently, it has become a way of leveraging the design data for yield learning and root-cause analysis—a process called diagnosis-driven yield analysis.
To manage yield at the mature production stage, traditional methods like test chip and PFA are effective, but expensive and cumbersome. The memory-failure bit-map method is limited in dealing with a logic-related yield issue. And the obvious systematic issues are normally resolved in the yield ramp-up stages. During mature production, however, the yield limiters can behave more like random defects. They are “hidden” in the baseline background. As a result, we need a large sample of failed die to improve mature yield, which limits the PFA-based yield learning method.
Freescale Semiconductor recently adopted a diagnosis-drivenyield- analysis (DDYA) flow based on the Mentor Graphics Tessent® YieldInsight™ tool (see Figure 1-1). It has proven to be economical and easy to use. Diagnosis-driven yield analysis works well for yield improvement at different stages. It also provides great benefit in the mature-yield-improvement domain.
During manufacturing test, volume-failure data logs are collected for the targeted lots and wafers. It’s recommended to collect 1000 or more failure die for mature yield analysis. Design image—including netlist and layout data (LEF/DEF), test patterns, and failure data—is used to perform volume layout-aware scan diagnosis. This layout-aware diagnosis analyzes the net topology for the suspect segments and eliminates false bridges and unjustified opens.
Compared with non-layout-aware diagnosis, it provides much better diagnosis resolution based on physical features. For example, the layout-aware diagnosis can report (x, y) coordinates of a potential bridge location between two nets on a certain layer (e.g., M2), rather than giving out all of the nets as suspects. In addition, it gives information for suspect ranking, critical area, and defect searching (encircle) area. This greatly reduces the PFA searching space and provides valuable classification for statistical analysis. Hence, it enables diagnosis-driven yield analysis.
An analysis database (ADB) is created upon diagnosis completion. It contains the failure datalog information and layout-aware diagnosis results. The database is analyzed statistically by the yield-analysis tool to look for yield signatures and identify the root causes. Yield signatures and root causes in different formats are reviewed. In addition, the physical failure suspects are examined in the embedded layout viewer. One also can drill down to find out the best PFA suspect candidates with high-diagnosis resolution from a few die, that represent the identified yield signatures and root cause. Unlike the traditional flow, in which yield-signature and root-cause analysis are based on PFA results, PFA in this flow is performed only on a few die. The purpose is to validate the finding and conduct construction analysis. After PFA, the correspondent corrections will be applied to new designs or for the purpose of improving yield.
The yield loss induced by device failure could be caused by the sensitivity of certain library cells, physical features like open net segment and bridge layer, or a specific location. With diagnosisdriven yield analysis, one can analyze more than 70 different yield signatures. Each signature can have hundreds of features. For example, a via macro signature analysis will include analysis for via1, via2, double via1, double via2, etc. It’s possible to selectively analyze a specific signature or do a complete analysis with one mouse click. Upon completion, the signatures—if any—will be shown in a console area. Different color schemes represent different levels of possibilities of yield limiters.
Figure 1-2 shows one of the typical yield-signature-identification and root-cause-analysis methods. From a random-defect distribution wafer map, the volume layout-aware diagnosis discloses that some die have bridge suspects on different layers (e.g., from M1 to M5). At Freescale, the wafer map was divided into three radial zones (center, middle, and outer). For a baseline random-defect issue, the distributions of the bridge defect pareto should be consistent across the radial zones for different layers. If bridge M2 has higher occurrences in the outer zone than others, the distribution trend is broken. A bridge M2 outer-zone yield signature is then identified. Further analysis of suspect types for the die in the outer zone shows that the side-by-side M2 bridge is the root cause. However, either the signature or root cause was hidden from the initial wafer map. There are a total of eight types of zonal analysis that a user can perform.
A few die are picked as PFA candidates. They have high-diagnosis resolution and best represent the yield signature and root cause (i.e., the side-by-side M2 bridge). High resolution means a high suspect score and minimum number of suspects (ideally, just one suspect) for the die diagnosed. After finding this bridge yield signature, one can filter out the related die and continue analysis on the remaining die. This can be a recursive process until all of the significant signatures are found and root causes are analyzed.
A high-volume, 90-nm design had a 95% mature yield from manufacturing scan test. Our goal was to bump it up by even a portion of that percentage in a few weeks. Traditional yieldanalysis methods showed that the current mature yield loss was caused by random (baseline) defects. Any further analysis proved to be very time-consuming and expensive.
For diagnosis-driven yield analysis, about 1300 failure files were collected from three targeted lots (lot1, lot2, and lot3) containing 50 wafers. Each failure file represented a die that failed manufacturing scan test. Some were scan-chain failures while some were scan-logic-only failures. Each logic-only-failure datalog had up to 256 failing cycles. More failing cycles were collected for chain failures. Because the datalog collection overhead was under budget, the volume layout-aware diagnosis was affordable. Although chain diagnosis doesn’t necessarily need layout-aware diagnosis, it is compatible with layout-aware diagnosis flow.
The volume layout-aware diagnosis for all 1300 die was done in batch mode. An ADB was created accordingly. The initial wafer map showed a random failure distribution. Next, the diagnosis resolution was checked by looking at its symptom and suspect paretos. The resolution was good because single symptom and suspect die represented roughly 70% and 13%, respectively, of the total die under analysis. That was better than the 50% and 10% threshold seen across industries. Good diagnosis resolution indicated that the following yield analysis was statistically meaningful.
First, a new analysis population was created, focusing on the scanlogic- only failed die (around 700). All signatures and their features were then analyzed across all of the zonal types with one mouse click. When the analysis was done, the possible yield signatures were reflected in the dashboard (the console area) and flagged by different colors (the darker the color, the higher the possibility of a systematic issue). In this case, the “Suspect Region: Count of Die” was flagged as a higher possible yield signature in zonal type Y (see Figure 2-1). This meant that defect locations were sensitive to a specific layout region.
The suspect region feature pareto showed that 30 die were more sensitive to a feature area (see Figure 2-2). The majority of them were due to open layers M2/M3/M4/M5 and via macros VIA2/ VIA3/VIA4, based on “Open Layer: Count of Die” analysis. This analysis indicated that these open layers were the potential root cause of the yield loss. The wafer map of the 30 die showed that the top Y region was highly correlated with the hotspot, shown in Figure 2-2 and Figure 2-3. We picked a die (die1) from lot 3, which had one diagnosis suspect and contained the signature in Figure 2-4. The layout view of die1 is shown in Figure 2-5. The other two lots weren’t available for PFA.
After filtering out the 30 die sensitive to the layout region, another round of similar analysis was performed for the remaining scanlogic- only die. Two more signatures and their root causes were identified: signature2 for open M3 and signature3 for open M1, VIA12, and M2. Accordingly, the drill-down process helped pick die2 for signature2 and die3 for signature3 (see Table 1).
After yield analysis on scan-logic-only failures, analysis was done for the remaining 500 or so chain failure parts. The fourth signature “chain cell number: count of die” was identified (see Figure 3-1). From the R2 zonal type, the die were selected from the top feature pareto chart in Figure 3-2. The drill-down from the wafer map helped pick two die (die4 and die5) for PFA (see Figure 3-3).
A total of five die were picked from four signatures as shown in Table 1. Three PFA results are shown in Figure 4.
With the above methodology, a process correction was made based on the three PFA results that improved the mature yield by 1.5%--three times better than the initial goal. All of this work was done in a few weeks, which the traditional yield-analysis method was unable to achieve.
Clearly, diagnosis-driven yield analysis has broken through the bottleneck of improving yield during the mature production stage. With layout-aware diagnosis as the enabling technology, this new methodology analyzes volume diagnosis results systematically and thoroughly. By looking for yield signatures and identifying root cause, it significantly increases the PFA hit rate for validating the systematic issue. Its follow-on correction processes have been very productive. This analysis approach has been proven to be effective while requiring much less cost and time.
Wu Yang is a technical marketing engineer at Mentor Graphics. He has 12 years of experience in DFT, test, diagnosis, and yield analysis. Yang holds a masters degree in electrical engineering from Portland State University. He can be reached at firstname.lastname@example.org/503-6850304.
Cynthia Hao is the DFT methodologist in the Technology Solutions Organization of Freescale Semiconductor Inc. She has over 12 years of experience in the semiconductor industry including five years of management roles. Her research interests include DFT and test. Hao holds a masters degree in electronic engineering from Xian Northwestern Polytechnical University, PR China. She can be reached at Pingli.Hao@freescale.com/512-68056679.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446