Until recently, the recognition that power needs to be understood early in the design process has been almost entirely at the most advanced process nodes. In mobile devices where a battery is the only source of energy for most of a day, that decision is easy to justify.
What’s changing, however, is the recognition that power now needs to be considered in the total system—not just the chip. And that has put pressure to begin understanding the implications of all power and how it fits into a global power budget even for chips designed at older process nodes.
There is no shortage of companies racing to fill this gap. The latest announcement by Apache Design is a case in point. Apache’s RTL Power Model is aimed at predicting power behavior at the RTL level and how that affects the overall design. This will become even more important in 2.5D and 3D stacking schemes, where power needs to include everything from layout to packaging.
Apache has added in data mining and pre-characterization, as well, which helps sift through the immense amount of data that needs to be considered in designing new ICs. This helps bridge the gap between having enough data to make intelligent decisions and raising the level of abstraction to be able to get a design out the door on time.
“Even with one customer there may be 12 different modes of operation, which is causing complexity in terms of verification,” said Vic Kulkarni, senior vice president and general manager at Apache. “That’s causing complexity in terms of verification. It’s also making it difficult to do planning for a realistic power distribution network. On top of that, packaging engineers are being ignored or they’re designing a package at the last minute.”
He said the result is frequently overdesigning for the worst case, electromigration from poor designs, or even power network collapse.
“For a large number of designers the solution is to add new RTL to reduce power, but there is no way to analyze that now without regression testing,” he added. “By looking at the power network the RTL level you can save a significant cost due to overdesign of the power grid, you can select the right package, and with better frame selection you can get a 10 to 30 times speedup vs. time-based power analysis.”
Apache is hardly alone in this quest, of course. All of the major EDA vendors are much more focused on power than in the past. High-level synthesis, which initially was aimed at making tradeoffs for processor cores, memory and IP, now is being re-targeted at power issues. Software prototyping increasingly is being targeted at improving the efficient interaction between hardware and software. And test has moved from simply whether a circuit works to how efficiently it works. The foundries also have stepped up their efforts on the manufacturing side, adding low-power and ultra-low-power processes to even older process nodes.
How all the pieces will work together in both mainstream and advanced flows remains to be seen, but at least there is a recognition that there is both a need—and an opportunity—to address power issues at all level of IC creation.