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DRAM Server Roadmap Points to DDR4 and 3D
Once upon a time, the DRAM server roadmap was predictable, as memory vendors simply marched down the natural progression of DDR interface standards.Now, the DRAM server roadmap is muddled with both DDR and 3D chip schemes to address a major problem: The industry is scrambling for a new, low-power DRAM solution to help tackle the soaring bandwidth requirements — and power consumption rates — for servers in the datacenter. DRAMs provide fast data access times, but they are falling behind the I/O curve and require heat-generating refresh cycles.
DRAM vendors are shipping products based on the DDR3 interface standard and are gearing up for new, lower power DDR4 technology. Driving a wedge in the roadmap are the first 3D products based on through-silicon-vias (TSVs), which are supposed to boost the bandwidth speeds but lower power consumption.
Going 3D also dodges the perceived scaling limitations for DRAM, which may hit the wall at the 1xnm node. There are several and rival 3D-like DRAM technologies on the table: Hyper Memory Cube (HMC); high bandwidth, wide I/O, among others. (more)
http://semimd.com/blog/2011/11/03/dram-server-roadmap-points-to-ddr4-and-3d/
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