The two major FPGA houses — Altera Corp. and Xilinx Inc. — are bitter rivals in the market.

Altera and Xilinx have different design philosophies and concepts. In the 2.5D/3D chip world, Xilinx has already announced its first 2.5D FPGA. Altera is working on unannounced 3D-like devices in the lab.

Both FPGA companies can agree on one thing: The industry must continue to bolster 2.5D/3D chip technology and the associated supply chain to enable these next-generation designs.

“The infrastructure is not mature enough,” said Brad Howe, vice president of IC engineering at Altera. “People are working on the infrastructure. We’re not there yet.”

Howe also expressed another concern in the 2.5D/3D chip arena. “The biggest challenge is power,” he told SemiMD in an interview at the 3D Architectures for Semiconductor Integration and Packaging event in Burlingame, Calif. on Tuesday (Dec. 13).

Ivo Bolsens, senior vice president and chief technology officer of Xilinx, issued a “call for action” in the 2.5D/3D chip space. “The industry still has work to do,” warned Bolsens during a keynote at the event.

To enable a successful run in the 2.5D/3D chip era, the industry must continue to address several issues. This includes the thermal problems, TSV-induced device stress and how to deal with the microbumps in these designs, he said.

The industry must also continue to develop the supply chain, he said. Along with the price delta between 3D devices and today’s chips, the supply chain remains unsettled and under stress. The unresolved questions include which vendor will be in charge of the bill of materials, inventory, integration and related functions. No one is clear about which vendor is in charge of the yields.

“Industry standards are badly needed,” he added. For example, there is a debate brewing over a 3D design-for-manufacturing (DFM) or design-for-test (DFT) standard. Within the IEEE, a relatively new entity — the 3D Test Working Group — is hammering out a proposed standard called IEEE 1838. The proposed standard hopes to define the architecture and description language for the “test access” architecture within a 3D device. The test access architecture is critical, because it can be used to test and ensure the quality of a 3D device during the IC flow.

As reported, Xilinx is shipping its 2.5D FPGAs, putting Altera in a rare position of being behind its competitor in the arena. Altera’s Howe said the FPGA house is developing products in R&D, but he did not elaborate.

Howe, who is scheduled to present a keynote address at the event on Wednesday (Dec. 14), said he will not announce products at the conference and did not comment on its 3D technology plans. He dropped hints that he may show a slide that depicts a 3D-like “heterogeneous die,” which could include an ASIC, FPGA, memory and a processor.

Altera has a slightly different view of the market than rival Xilinx. To a large degree, Xilinx’ FPGA is a somewhat homogeneous device. “You can use homogeneous dies and scale the platform,” he said. “Scaling is one (aspect), but it’s one of many.”

The large FPGA houses will not only push 3D-like technologies, but they will continue to move down the process technology curve and jump on the finFET bandwagon. In other words, 3D-like technology and leading-edge planar devices may co-exist.

At present, Altera and Xilinx are shipping 28nm devices based on a 2D planar transistor structure. Another vendor, Achronix Semiconductor Inc., will shortly ship its FPGAs built on a new, 22nm transistor architecture from Intel Corp. Last year, Achronix struck a deal under which Intel will provide foundry services for the FPGA startup. Intel’s 22nm process makes use of a tri-gate transistor technology – or finFET.

“All FPGAs will be based on finFets some day,” Howe said, saying the technology provides benefits in terms of power and performance.

The silicon foundries, including TSMC, are not scheduled to bring up its finFET technology until the 14nm node. Altera uses TSMC as its sole foundry. Xilinx uses both TSMC and Samsung as its foundry partners.