Published on December 19th, 2011
Now tell me how many of them can be thrown at a highly congested, hierarchical design at low process nodes, with all of the complex design rules you can think of, that will deliver a really efficient top level routing result in terms of completion, quality of results and DRC correctness?
If my experience at DAC this year is anything to go by, the answer to the first question is “a lot,” and the answer to the second question is “hardly any.“
There are many very capable routing tools on the market. There are the “industry standard” routers, which are gridded routers that will route very large digital cores using parallelization on big server farms very quickly and effectively.
There are a small handful of capable custom routers, typically shape-based, that will handle a highly congested, structured design like a memory (DRAM/NAND/NOR etc.), FPGA, LCD/LED or other structured IC design; that will route extreme aspect ratio designs with no jogs; that will route multiple buses or datapaths; and that will handle the job quickly and efficiently enough that you don’t have to spend an entire week after routing doing manual clean-up.
There are also some specialist routers that will route analog designs, but, by and large, their functionality is limited and they are either hybrids or evolved from a router originally designed for other market segments.
But when it comes to addressing the challenge of routing the top level of a highly congested, hierarchical design with many physical routing layers -- areas where routing has to be compressed or where pins have to be (intelligently) sorted to avoid nets crossing; where multiple nets have to be routed with a specific topology between many cores in a multi-core design; that involves routing of buses or datapaths with repeaters, different shielding policies for different nets or groups of nets, different spacing and bias on each layer, layer costing constraints…(and the list goes on) -- there’s has been no solution to the challenge. Until now.
As custom ICs grow in capacity and functionality, designers are forced to find creative ways of accommodating heavily congested designs with multiple layers of hierarchy. The task of routing all blocks concurrently, while trying to resolve congestion at each level of hierarchy and simultaneously route inside and between blocks, is a daunting challenge. Add to this the fact that design schematics change until just before tape out, and the problem is compounded by having a moving target at late stages of design closure. Consequently, the impact of netlist changes can be significant because routing may have to be redone to accommodate logic changes.
The problem has been exacerbated because more and more functionality is being crammed onto custom ICs, which means more layout work is required to complete the design. Design teams are being forced to use more discrete teams to completely address the problem, but without a structured, automated approach, it is becoming more difficult to complete the integration of the results of these tasks manually.
There was no solution that addressed the problem of routing to a very high completion rating, DRC-correct with all of the constraints being met. Until now.
So, what’s the secret recipe for solving the problem? Well, first you need to find a router that is designed to solve a specific problem. Don’t try to “adapt” an existing product that does another routing task well, because an effective and productive signal planner needs to have a unique set of features and functionality.
The “must haves” to look for include the obvious requisites:
But other important attributes include looking for a router that is seamlessly integrated with a block placer and pin placer, tuned to solve the specific multi-topology routing. Add to that the ability to do fast prototyping, net sorting, multiple bias routing and specialized topology routing and you’ll have a pretty good starting point to solve the problems of hierarchical signal planning.
Dave Noble, Vice President, Operations North America, Pulsic, Inc., has been CEO and COO of several software startups in the U.S. and U.K. including an EDA distributor in southwestern U.S. prior to joining Pulsic in 2004.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446
Hyatt Regency - Santa Clara, CA July 26 - 27, 2016