Published on January 03rd, 2012

Full-Speed Hardware Validation Platform Now Mimics High-Speed Serial Analog Interfaces

The third generation of Arasan Chip Systems’ Hardware Validation Platform (HVP) adds the ability to perform early validation of a new interface by emulating the complementary device at the interface protocol level. The system can validate the hardware and software infrastructure that complies with the analog PHY based standards for serial connectivity between chips, camera and display modules, and flash storage in mobile platforms. The validation platform also eases the early application development for reference board designs and production testing, well before complementary devices are available in silicon. Thus, designers adopting emerging and existing protocols such as the MIPI Unipro (mobile industry processor interface, unified protocol interface), CSI-2 (camera serial interface), and DSI (display serial interface), as well as the JEDEC UFS (universal flash storage) and SDA’s (Secure Digital Association) SD4.0, can now leverage Arasan’s validation platform to jump-start and accelerate their pre-silicon and system validation and application development.

In the product cycle, the HVP gen 3 acts as a reference platform to help root-out any incompatibilities between the device under development and the silicon device it is designed to communicate with. To do that, the new platform offers full-speed hardware validation by combining a robust hardware platform with a rich collection of interface intellectual property that can overlay on a high-performance FPGA-based customizable interface and a connectivity board. That combination allows the platform to match the signaling levels and protocol to the host system at full speed and at a relatively lower cost than other hardware verification platforms that use large arrays of FPGAs and often cannot run at the full system speed of the target device.

The previous generations of these verification/validation platforms address verification challenges for interface protocols that require digital interfaces, like MIPI’s SLIMbus and HSI, and SDA’s SD3.0. The new Arasan platform delivers all the capability of the previous-generation systems along with rich runtime tracing and debug capabilities. Additionally, the third-generation platform family extends these capabilities to complex protocols that require analog PHY layer interfaces like MIPI’s D-PHY and M-PHY, and SDA’s UHS-II. UFS and the upcoming MIPI LLI and CSI-3 interfaces are based on the MIPI Unipro link protocols, which are complex and multi-layered in both hardware and software.

The hardware validation platform for SD4.0, CSI-2/DSL, Unipro, and UFS will be available in the first quarter of 2012. Arasan Chip Systems Inc., San Jose, Calif., (408) 282-1600

Dave Bursky is a contributing editor for Chip Design and Chip Design Trends. He also is the technical editorial manager at Maxim Integrated Products Inc. in Sunnyvale, CA.



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