Solving the SoC Design Enigma with IPIncreasingly semiconductor companies are experiencing the intricate design challenges of building next-generation SoCs.
Since companies can't build all their own IP, they must focus internal investments on technology that will give them a unique differentiation in the market and team with strong design partners to license the remaining pieces. It has often been quoted that for every dollar of IP that is licensed it costs about two to five dollars to use. So clearly a large part of the “make vs. buy” decision is finding well qualified IP vendors that will help to effectively minimize the cost and time of IP integration. Once a buy decision is made, there is a lot of work to do and questions to ask:
1)What is the maturity of the IP (i.e. quality/reliability)?
2) How will it perform in the target process node?
3) How can IP blocks from multiple vendors be easily integrated?
4) What is the business model?
Fortunately IP, design tools suppliers and foundries are getting a firm grasp on the challenges that customers face when trying to specify and assemble complex SoCs. Several companies are starting to work together to create a more seamless flow from IP selection, system design and back-end manufacturing. A recent example of this is the soft IP Quality Initiative being driven by TSMC and Atrenta. They are working with 10 IP suppliers as part of a soft IP alliance program to qualify the RTL deliverables of the suppliers. This initiative gives SoC developers a true peace of mind along with time-to-market advantages knowing that IP has been qualified and run through rigorous steps at the RTL level. This is a critical step, but is it enough for the overall SoC creation? Assuming that you did a solid job selecting well qualified IP, the next challenge is having the ability to integrate all of these disparate IP blocks and use them in a way that will deliver the maximum system performance and efficiency.
A critical IP block that is now at the center of the make vs. by decision is the on-chip network, or fabric, that connects all of these IP blocks together. SoC design companies are finally concluding that connecting 40, 80 or well over 100 cores together is a major challenge to design and verify in a timely manner. Difficulties stem from the fact that each IP core is likely to have a different interface protocol (AMBA, OCP, proprietary, etc.), different bit widths, different frequency and different power requirements.
In addition to connectivity, the performance of the overall system is greatly impacted by the design of the network since all of these heterogeneous processor cores will be competing for memory bandwidth. The network will have to deal with the overall quality of service, error management, security and even system coherency in some of the more advanced designs. Selecting the right network with all of these features is an essential step to ensure the system meets the stated performance goals and can execute on schedule. Since the on-chip network is the ‘nervous system’ of the SoC, with the correct design tools, this is not only a critical IP block, but a platform methodology that will allow SoC designs to scale as requirements change--ensuring the fastest time-to-market with incremental and new designs.
So are advanced SoCs difficult to design? Yes, as you can see from some of the challenges outlined. However, real strides are being made by IP and tools manufacturers to assure the quality of the IP. In addition to quality, adopting an on-chip network platform methodology is becoming a key part of executing a successful SoC strategy -- allowing any third party IP from any source to be easily connected to the network. This methodology will help reduce that two to five dollar cost of IP integration and help companies remain competitive in the fast growing markets that require complex SoCs.