3D Chip Mania Grows but Mass Adoption LagsIBM group takes step forward in 'true' stacking
The 2.5D/3D chip era continues to gain momentum, as Altera Corp. this week made a major announcement in the arena. Indeed, the advent of 2.5D/3D chips based on through-silicon vias (TSVs) is considered a “game changer” in the semiconductor market, but mass production for the technology is still a moving target.
At this week’s “The Heat is On 2012” conference in San Jose, Calif., one analyst said 3D TSV chip volumes are at least two years away. Another expert at the event said a “true” 3D chip — which combines processors, memory and other functions — is still a decade away due in part to thermal issues. But a team of IBM Corp. and Swiss researchers will shortly roll out a test chip that could accelerate the shift to “true” 3D devices. The group is devising a 3D stack with a functionality per unit volume that nearly parallels the density of a human brain.
Implying that 3D TSVs are too expensive and difficult to make, still another expert said that there is sudden interest for multi-chip modules (MCMs) based on a new class of organic substrates. And at a recent and separate event, one presenter from a company said that he is actually telling customers not to develop 2.5D/3D chips.
So what’s the deal? For years, the industry has been talking about 2.5D/3D chips as the next big thing in the semiconductor industry. Frankly, however, it’s taking longer than expected for 2.5D/3D chips to enter volume production. Cost and supply chain issues remain a hurdle. The lack of EDA tools, thermal challenges, the tough temporary bonding/debonding steps, and test are among the technical challenges.
Still, integrated device manufacturers (IDMs), foundries and packaging houses have or will put 2.5D/3D TSV capacity in place in an effort to prepare for demand in the market. But most — if not all — vendors “are still waiting” for the first wave of demand, said Jim Walker, an analyst at Gartner Inc.
In terms of mass production for 2.5/3D TSV devices in the market, the “volumes are still a couple of years away,” Walker told SemiMD at the “The Heat is On 2012” event. The conference was by sponsored by the Microelectronics Packaging and Test Engineering Council (MEPTEC).
He was quick to point out that there have been a smattering of 3D TSV announcements in recent years. For example, Toshiba Corp. has shipped CMOS image sensors based on 3D TSVs. Samsung Electronics Co. Ltd. has shipped a 3D TSV DRAM module. IBM Corp. has shipped RF devices built around the technology. And more recently, Xilinx Inc. has begun shipping an FPGA built around a 2.5D interposer technology.
Walker expects a new class of 3D DRAMs for use in file servers will begin shipping in the second half of 2012. He was alluding to the Hybrid Memory Cube (HMC), a 3D TSV memory technology being developed by Micron Technology Inc. and Samsung.
Perhaps the biggest development is Xilinx, which is shipping a 2.5D FPGA. Rival Altera this week announced a similar effort. Both Altera and Xilinx will have their respective devices built on a new turnkey line at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC). As reported, TSMC’s 2.5D/3D line, dubbed Chip-on-Wafer-on-Substrate (CoWoS), is surprising to some observers: It is providing an end-to-end solution, including all of the traditional assembly and test steps handled by the IC packaging houses.
TSMC argues that it can provide better yields if it controls the entire supply chain. Others believe TSMC is looking to capture some margins – at the expense of the IC packaging houses. “I think it’s too early to tell” if TSMC’s CoWoS strategy will work, Walker said, but clearly, “TSMC wants to get its hands in the cookie jar in IC packaging.”
TSMC’s strategy appears to be somewhat different from GlobalFoundries Inc. and United Microelectronics Corp. (UMC), both of which have not announced their 2.5D/3D strategies. Walker believes GlobalFoundries and UMC will provide the traditional front-end steps “up to TSV middle,” and then they will hand off the conventional backend work to the IC packaging houses.
In any case, the lines are blurring in front-end production and packaging. “A year ago, people were wondering if the packaging houses would get into the (3D TSV) business,” said Sesh Ramaswami, managing director of strategy for the Silicon Systems Group at Applied Materials Inc. “Now, many OSATs are getting into the TSV business.”
The bigger IC packaging houses, including Amkor, ASE, Powertech, SPIL, and STATS, have added front-end capacity to handle 2.5D/3D TSV production. The packaging houses do not offer fine-pitch TSVs, but they can provide technology for the development of MEMS, RF devices, and related devices.
In a recent interview, Ramaswami said the 2.5D/3D chip business remains in its infancy. “It is still in the early stages. If you look at the players, they are shipping engineering samples. Customer samples are starting at the end of the year. Some production will start in the second half of 2013,” he said.
‘True’ 3D chips are far away
Others believe that it’s later rather than sooner. “The road to ‘true’ 3D is at least 10 years away,” said John Thome, project leader for the Swiss Nano-Tera CMOSAIC Project. In 2010, IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) signed a four-year collaborative project called CMOSAIC to understand how the latest chip cooling techniques can support a 3D chip architecture.
IBM and others are devising a 3D brain chip (Source: CMOSAIC)
The CMOSAIC project considers a 3D stack-architecture of multiple processor cores with a interconnect density from 100 to 10,000 connections per millimeter square. Researchers believe that the use of hair-thin, liquid cooling microchannels measuring only 50 microns in diameter between the active chips are the missing links to achieving high-performance computing with future 3D chip stacks.
The CMOSAIC project is attempting to devise a 3D stack of computer chips with a functionality per unit volume that nearly parallels the functional density of a human brain. CMOSAIC’s goal is to provide the required 3D integrated cooling system that is the key to compressing almost 1,012 nanometer-sized functional units (1 Tera) into one cubic centimeter with a 10 to 100 fold higher connectivity than otherwise possible.
Even the most advanced air-cooling methods are inadequate for high performance 3D-IC systems where the main challenge is to remove the heat produced by multiple stacked dies in a 1-3 cm3 volume, each layer dissipating 100-150 W/cm². 3D chips are the wave of the future, but they suffer from “heat flux accumulation, additional thermal resistance and peak temperatures,” Thome said during a presentation.
At the “The Heat is On 2012” conference, Thome provided an update of the project, which is devising both single- and two-phase interlayer cooling methods using refrigerants for 3D stacked processors. IBM has devised a single-phase liquid impingement technology for use on the chip backside. This is capable of cooling power densities of 400 W/cm² – six times more than the current limit of air cooling and two times the current processor design limitation of 200 W/cm², according to IBM.
During his presentation, Thome said the industry is moving towards two-phase interlayer cooling. This idea is to use thermal properties of liquids and two-phase flows to mitigate the thermal issues and cool a system. The advantage of two-phase is that “cooling up to 200-300 W/cm² is achievable,” he said. Other advantages include high-latent heat of vaporization (about 150kJ/kg) and lower mass flows, he said.
Test chip from CMOSAIC (Source: CMOSAIC)
In September, the project is expected to complete its first test chips — a move that could accelerate the development of “true 3D” chips in the market. Measuring 1- x 1- x 1-cm, one test chip is a stacked, 50-layer device that will incorporate a two-phase cooling method and TSVs at 60 microns in diameter and 200 micron pitches. Meanwhile, the other test chip will include TSVs with the same dimensions, but it will use a silicon interposer technology and will incorporate both single- and two-phase cooling technologies.
Back to the future
“3D has thermal challenges,” said Ivor Barber, director of package design and characterization at chip maker LSI Corp., in a brief interview at the event. “It also has architectural challenges.”
For that reason and others, chip makers and system houses are rethinking their push into 3D. Instead, they are looking at an older technology that could prove to be more cost-effective than 3D TSVs in the short term: MCMs.
“There is a renewed interest” in MCMs based on a new class of organic technology, Barber said. Ibiden, Kyocera, Samsung, and Shinko have developed a new class of organic laminate substrates for chip applications.
Shinko's so-called coreless organic substrates (Source: Company)
Last year, for example, Shinko started volume production for a new line of so-called organic, built-up substrates . Dubbed DLL, Shinko’s substrates are manufactured by alternately forming insulator layers and copper plated circuit layers simultaneously on both sides of the structure.
Every insulator layer has laser-formed “micro vias” to electrically connect the copper circuit layers on each side of the insulator layer. In addition, the core layer has numerous mechanically drilled and copper plated through-holes to electrically connect the top and bottom sides of the core to the build-up layers. Shinko and others have recently outlined their roadmaps in the arena.
Shinko's new substrate enables ASICs, MPUs (Source: Company)
Cross section of Shinko's DLL and DLL3 organic substrates (Source: Company)