New DFM and Verification Hurdles Seen at 20/14nmDouble patterning poses new challenge
For years, the shift to the next process node has always presented new, difficult and sometimes costly challenges in the IC manufacturing flow.
At the 130nm node, for example, chip makers saw the ongoing migration to sub-wavelength lithography, the transition to low-k dielectrics, and the emergence of design-for-manufacturing (DFM). And at that node, there were also two basic physical verification steps in the flow: one-dimensional design rule checks (DRCs) and layout versus schematic (LVS).
At the time, the 130nm node seemed like a difficult process to master. Fast forward. As the logic world migrates from the 40nm to the 32/28nm process nodes, chip production is obviously more complex and expensive. At 32/28nm, for example, the foundries must extend 193nm wavelength lithography and implement their initial high-k/metal-gate schemes.
From a physical verification standpoint at 32/28nm, IC makers will continue to use the old standbys: DRC and LVS. But starting at the 40/28nm nodes, vendors added more complex physical verification steps to the mix: 2.5/3D verification, parasitic extraction, advanced device parameter extraction, lithography checks/simulation, patterning matching, dummy fill, among others.
And if that wasn’t enough, there are even more challenges at the 20nm node and beyond. IC design, process and fab tool costs will continue to soar. From a DFM and physical verification standpoint, chip makers will also face some new challenges. Among the newer physical verification steps— and challenges— at 20nm and 14nm include double-patterning, delta-voltage DRC, advanced fills, design-for-reliability (DFR) and others.
“At every technology node, the designer must address more and more manufacturability concerns,” said Michael White, product marketing director for Calibre Physical Verification at Mentor Graphics Corp. “This has manifested itself as an increase in DRC checks as well as other verification checks node over node.”
Here’s some of the newer physical verification steps that chip makers will face at 20nm and 14nm:
Double patterning: Not a show stopper (yet)
The biggest step from the 28nm to the 20nm node is clear. “Double patterning is the major thing at 20nm,” said Andy Brotman, vice president of design infrastructure at silicon foundry vendor GlobalFoundries Inc.
Brotman believes the industry is ready for the double patterning era at 20nm. But at 14nm, it’s unclear if extreme ultraviolet (EUV) lithography will be ready in time. If not, the industry must extend 193nm immersion and may be forced to use triple-patterning. “Double-patterning is doable,” Brotman said. “For triple-patterning, there is work to be done.”
In other words, chip makers face the dreaded multi-patterning era as they march down the process curve. On the device side, the SanDisk/Toshiba duo are ramping up the industry’s most advanced process – a 19nm NAND flash line. On the logic front, Intel Corp. is moving from planar transistors at 32nm to finFETs at 22nm. At 20nm, the foundries will continue to use planar transistors. The foundries plan to move to finFETs at 14nm.
To continue scaling, the NAND crowd has already inserted a technology called self-aligned double-patterning (SADP). At 20nm, the logic vendors are looking to adopt a relatively expensive double-pattering technique called litho-etch-litho-etch (LELE). Double-patterning “is a very complex step,” said Mentor’s White. “But all of my competitors are saying: ‘Double patterning is here and the sky is falling.’ Will this be a giant (show stopper)? I don’t think so.”
|Two types of double patterning flows (Source: Mentor)|
So, at least from a physical verification standpoint, double patterning is doable, he said. On average, the number of physical verification steps are increasing by some 30 percent at each process node. There are a total of 3,000 individual physical verification or DRC checks at the 32/28nm node, according to Mentor.
In comparison, there are a total of 3,500 checks at the 20nm node, a 30 percent increase from 32/28nm. But surprisingly, less than 1 percent of those checks are related to double-patterning at 20nm, he said.
There are some challenges, however. In double-patterning, the layout patterns are split and decomposed into two different masks. The polygons or features are assigned different colors. If the features are too close, then so-called “coloring conflicts” may emerge. This can be solved by using cut and stitch techniques. In this scenario, the polygons on a mask are cut into different pieces and then recombined through stitching points.
“Using cuts in (an) auto decomposition tool can fix a majority of cycle violations but is adds complications in OPC correction and potentially more electrical variation,” he said.
At 14nm, it’s unclear if EUV will be ready in time. If not, leading-edge logic vendors are looking at triple-patterning or SADP. And there is also still uncertainty at the 10nm node. Some hope EUV will be ready at 10nm. Since EUV is a 13.5nm wavelength technology, EUV will likely be combined with double-patterning at 10nm. Another technology called directed self-assembly (DSA) could swoop in and save the day.
Summarizing the trends in lithography, White said: “Multi-pattering is here to stay.”
Voltage-based DRC technology
At the 20nm node, most of the attention is currently centered around the emergence of double patterning. But there are new technologies emerging at 20nm, namely delta-voltage or voltage-based DRC.
DRC technology verifies the layout of a circuit and ensures that the design does not violate any rules associated with the process. Over time, Mentor has developed equation-based DRC, which allows users to check and correct issues that are difficult to perform with classic DRC. This includes gate and interconnect checking, poly corner rounding, among others. “DRC has been around forever, but it gets harder and harder,” White said.
At 20nm and 14nm, there is expected to be the emergence of voltage-based DRC. “You want a larger spacing between nets, where there is a large voltage differential (e.g. between ground and 5V). You can afford a smaller spacing between net with less (e.g. ground and 1.5V or between 1.3V and 1.5V),” White said. “Some of these types of checks were in place at 28nm, but they always assumed the worst case (e.g. ground and VDD). At 20nm, they are more sophisticated.”
Don’t forget about DFM
For some time, a designer has only had two options for identifying DFM issues in the design phase: run accurate but computationally intensive simulations or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success.
To solve the issue, GlobalFoundries has implemented a technology called DRC+. This goes beyond standard DRC and uses two-dimensional shape-based pattern-matching to enable a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy. DRC+, together with rule-based DFM verification and model-based litho/etch and CMP simulators, can identify new yield-detracting patterns.
Fill it up
In chip design, there is a step called fill. This involves adding shapes or polygons to the design, which ensures each layer has the proper density. One option for metal fill was sometimes called “dummy fill.” But dummy fill solutions become more challenging at each process node, requiring advanced or “smart” fill techniques at 20nm and beyond.
“That is, the fill must be ‘smart,’ meaning it integrates an analysis engine with the filling algorithm and performs analysis concurrently with fill insertion; a technique that qualifies as correct-by-construction,” said Jean-Marie Brunet, product marketing director at Mentor, in a recent blog posted on SemiMD. “The result is minimum fill, complete adherence to constraints, improved manufacturability, and a faster run time.”
Yet another DFx term is hitting the airwaves: Design-for-reliability or DFR. In design scaling, there are ongoing stress effects, electrostatic discharge (ESD) and other issues that crop up. In other words, there is a need for “comprehensive reliability checks,”Mentor’s White said.
Electrical rule checking has been around for some time to address ESD and other issues in designs. Still, there some vast changes taking place in ESD standards, prompting chip makers to re-think their strategies.
It has been widely known that ESD causes an inordinate percentage of chip failures in the field. For years, ESD target levels for chips in the human body model (HBM) and machine model (MM) have stayed constant at 2KV and 200V, respectively. But a group called the Industry Council on ESD Target Levels believes that these ESD levels are taking up too much silicon real estate, prompting the need for lower target levels. For some time, the group has proposed a reduction in ESD levels to 1kV for HBM and 30V in MM.
Some OEMs are moving to lower their ESD target levels. Others are reluctant to lower their ESD standards. What this implies is that chip makers must be flexible and have a sound ESD strategy, in additionl to the associated IP and EDA tools in place.
Solution to the problem: Go with the flow
“The challenge at 20nm centers around double-patterning and a lot of design rules,” said GlobalFoundries’ Brotman. “The question is how do we continue to shrink to 2xnm with more restrictive design rules?”
One of the solutions is to provide flexible options in the design flow. Mentor recently disclosed pieces of the 20nm design flow for the Common Platform alliance, which includes IBM, GlobalFoundries and Samsung.
There are four different options in the flow, each with a set of trade-offs. On one end of the spectrum, a colorless flow is more restrictive but also more automated. On the other end of the spectrum, there is a manual flow that is less restrictive. There are hybrid flows in between. “I would expect to see similar flows at 14nm and beyond,” Mentor’s White said.
|20nm design flow for Common Platform members (Source: Companies)|