Published on April 27th, 2012
CYCLE slip observed in a PLL during transient, is due to the cyclic nature of the phase detector. Papers that describe the analysis of PLL cycle slips are few, and those that are available are relatively complex.
In a PLL with a saw tooth phase detector (e.g., a PFD), cycle slip happens when the phase error is greater than |2π| rad. When this is the case, for example |2π+0.1| rad, the actual phase error seen by the phase detector is only |0.1| rad and the loop will think that the phase error has switched direction, thus switching its tuning direction too. The tuning profile of forward tuning VCO is shown in Fig. 1. This paper will only deal with PLL with PFD, as it is widely used
Transient will happen when it is required to change the output frequency of a PLL. Fig 2 shows the PLL diagram that use charge pump PFD and fractional N divider. To change the PLL output, the divider is programmed to a different value.
Charge pump PFD outputs current of Ipd for a given phase error of Éµerr. Kpd is the gain for the PFD. F(s) for the loop controller, Kv for the VCO, and 1/N.F for the divider. The output frequency Fvco is N.F*Fref. The 1/s factors at both PFD inputs are there as we are dealing with frequency at input Fref and at output Fvco.
Fig. 1. Cycle slips during PLL transient. A similar profile can be seen on Vtune.
Fig. 2. PLL block diagram.
Fvco can also be changed by changing the Fref, but this is uncommon in practice. Nevertheless, it is more convenient from an analysis point of view as the change is directly at the input of the PLL. For a PLL in Fig.2, the equivalent change at Fref when the divider is changed is given by (1). Nold is the old divider value and Nnew is the new divider value after stepping. The change ΔFref is in step, as the change in the programmable divider value is instantaneous.
Before this new PLL cycle slip analysis is explained, small signal transient must first be analyzed. Small signal is valid when the PFD’s phase error never exceeds |2π|, thus everything is linear and Laplace can be used. For a given input, the output is calculated by multiplying the input with the PLL’s system transfer function H(s), defined as the ratio of Fvco(s)/Fref(s) and is calculated in (2). The output response at Fvco is given in (3). The transient response at Fvco can be calculated in (4) by taking the inverse Laplace transform of (3).
As will be shown later on, the transient response at the output of the PFD must be analyzed to determine if cycle slip will occur. This can be done by multiplying the PLL’s error transfer function E(s) in (5), with the input. E(s) is the ratio of Ipd(s)/Fref(s). The transient response at node Ipd is calculated using (6) and (7).
The cycle slip analysis presented in this paper is mainly in the s-domain where the Laplace and inverse Laplace transform will be used. The paper is structured in the following manner. Section II describes the cycle slip condition. Section III will describe 1 cycle slip analysis. Section IV will cover the analysis for generalized n cycle slips. Section V compares the results using this new technique against ADS and Section VI concludes the discussion.
II. CYCLE SLIP CONDITION
When the equivalent change at Fref causes phase error Éµerr to be >|2π|, then linear analysis as outlined in Section I can’t be used. This paper will describe this can be done somewhat through linear analysis so that intuitive understanding on cycle slip could be achieved.
Instead of looking at the phase error to determine cycle slip, the current output Ipd of the PFD is used, as this is physically accessible for probing. Without loss of generality, the charge pump PFD will be used throughout this paper.
Charge pump PFD is actually a time discrete device instead of time continuous. The output toggles between 3 discrete values of Ipdpeak, 0 or – Ipdpeak amp. Even though it is discrete, the phase error information is analog as it contains the varying width of Ipdpeak or – Ipdpeak pulse. The wider the pulse is, the larger the phase error. Even though the phase error is analog, it is not time continuous, as the phase error information is only available at every 1/Fref period, thus disabling analysis in s-domain. To enable analysis in s-domain, the charge pump has to be modeled as a time continuous device. To achieve this, we can assume that the charge pump PFD outputs continuous current between – Ipdpeak to Ipdpeak, instead of discrete. As the phase error dynamic range of the PFD is -2π to 2π, the modulation gain of the PFD can then be defined as Kpd= Ipdpeak/(2π) whose unit is A/rad. At 0 phase error, the PFD output is 0 A and at the max phase error of 2π, the PFD outputs Ipdpeak A. So the max current at note Ipd as in Fig. 2 can only be Ipdpeak before the loop goes into cycle slip. This cycle slip condition, achieved by looking at node Ipd, will be used throughout.
III. ONE CYCLE SLIP ANALYSIS
A transient response with only one cycle slip will be first explained before generalization is done for n cycle slips. When cycle slip occurs, the current at Ipd will step from Ipdpeak down to 0 A for positively increasing phase error, or from – Ipdpeak to 0 A for negatively increasing phase error. Without loss of generality, positively increasing phase error will be assumed throughout the analysis. Equivalently, the phase error Éµerr will step down from 2π down to 0 rad. This phase step can also be viewed as a -2π step at the phase detector input, applied at the moment cycle slip occur. This different perspective of cycle slip is the key to this fast and new approach of cycle slip analysis.
When the N divider is stepped, the transient response at node Ipd can be first calculated using the linear response outlined in the Introduction section, regardless of whether cycle slip will or will not occur. This is shown in (8).
When the first cycle slip occurs at t = tslip1, this can be viewed as a phase step of -2π rad being applied at the input of the PFD at t = tslip1. To calculate the response at Ipd due to this -2π rad phase step, (6) can be leveraged with a slight modification as the input is now in rad rather than in Hz. The transient response can be calculated by first assuming that the -2π rad phase step is applied at t = 0, rather than at t = tslip1, and is shown in (9). The inverse Laplace is then applied on (9) and arrives at (10).
We then have to shift the transient response in (10) by +tslip1 on a time scale and force the response to be 0 for t < tslip1. This is shown in (11) where u(t) is a unit step function. The total transient response is the sum of the two transient responses as shown in (12). Fig. 3 illustrates the steps for more intuitive understanding.
Fig. 3. Illustrations of 1 cycle slip analysis.
For the one cycle slip case, finding tslip1 is straightforward as shown in (13). Caution must be taken when solving (13) as there can be 2 solutions; tslip1 is the time whereby ipd0(t) crosses Ipdpeak the first time.
So far we have only discussed the solution at node Ipd. The solution at node Fvco will take similar steps. Once tslip1 is figured out, the cycle slip analysis at any node is relatively simple. What follows are the steps for solutions at Fvco. The first step is to calculate the transient due to the equivalent change at Fref as in (14)
Next, we need to calculate the transient response when the cycle slip occurs at t = tslip1 where this is equivalent to having a -2π rad phase step applied at the input of the PFD. To simplify the analysis, it is assumed first that the -2π is applied at t=0, instead of at t=tslip1. The steps to arrive at the shifted time-domain response are shown in (15) and (16). The transient solution in (16) needs to be time shifted by tslip1. The response prior to tslip1 is forced to 0, as defined in (17). The total transient solution at Fvco is given in (18).
CONCLUSION FOR PART 1
The Part 2 of this paper will be covering the generalized solution for N cycle slip analysis and comparison with analysis from ADS.
Akmarul Ariffin Salleh (M’05) received his B.E. (Summa Cum Laude) degree from Vanderbilt University, Nashville, Tennessee, in 1999 in electrical engineering with a major in Mathematics. He joined Agilent Technologies in 2000 as a Network Analyzer Product Engineer. Since 2005, he worked as an R&D Engineer for Agilent Santa Rosa California, designing high-performance handheld network analyzers and spectrum analyzers.
His current research interest is on low phase noise, fast settling phase-locked loop frequency synthesis, and spur free Sigma Delta frac N.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446
Austin, TX June 5-9, 2016
Encore at the Wynn, Las Vegas June 12-15, 2016
Red Rock Resort & Spa - Las Vegas, NV June 23-24, 2016
Moscone Center - San Francisco, CA July 12-14, 2016
Hyatt Regency - Santa Clara, CA July 26 - 27, 2016