Will EUV Miss Another Node?Industry bracing for multi-patterning era
Extreme ultraviolet (EUV) lithography is late for the 10nm node and could possibly miss the window for that insertion point, according to a panel discussion at last week’s SPIE/BACUS Photomask Technology conference in Monterey, Calif.
The IC industry has various EDA, lithographic, photomask and other solutions in place If EUV remains delayed, but the challenges will continue to mount in the multi-patterning era, according to panelists at the event. The panel was entitled “Will optical patterning solutions be ready if EUV lithography continues to be delayed?”
During the panel and the SPIE/BACAS event in general, there were rumblings that EUV is delayed — again. Analysts believe that EUV may be too late for the 14nm node, but now there are growing fears that the technology is in danger of missing the 10nm window.
“It’s clear that EUV will be late for our 10nm node,” said Allen Gabor, senior patterning program manager in advanced lithography at IBM, during the panel.
In a brief interview after the panel, Gabor said IBM has not totally dismissed or counted out using EUV for the 10nm node. “If it is ready, we will use it,” he said, without elaborating.
During the panel, he presented a slide of what appeared to be IBM’s lithography roadmap. At 10nm, EUV and 193nm immersion are still in the mix. Other leading-edge chipmakers, including GlobalFoundries, Intel, Micron, TSMC, Samsung, SK Hynix, Toshiba and others, have not publically indicated that EUV will be late for 14nm or 10nm.
The sole EUV tool supplier, ASML Holding, is expected to ship its NXE:3300B, a full-blown, 13.5nm EUV production tool, later this year. In January, ASML promised an acceptable throughput of 69 wafers an hour for the tool.
Amid ongoing delays for the EUV light source from Cymer, ASML in July lowered its targets and promised a throughput in the “30ish” range in terms of wafers per hour this year. It’s possible that ASML may not deliver 70 wafers per hour for the machine until 2014, according to C.J. Muse, an analyst with Barclays Capital, in a recent research note.
Intel’s recent decision to invest as much as $4.1 billion in ASML has raised overall confidence levels in EUV lithography. TSMC and Samsung have also invested in the Dutch-based lithography giant. ASML has said it needs to reach 250 Watts of average source power to achieve the 125 wph throughputs sought by its early customers—roughly 10x today’s situation.
The IC industry hopes that EUV will be ready at 14nm. But if EUV misses 14nm, and is inserted at 10nm, it still could be an expensive solution. Since EUV has a wavelength of 13.5nm, EUV will require some form of a double-patterning scheme at 10nm, IBM’s Gabor said.
In any case, leading-edge chipmakers may be forced to extend 193nm immersion much further than previously expected. Chip makers will also utilize a double-patterning scheme, such as sidewall image transfer or self-aligned double patterning, litho-etch-litho-etch (LELE), or self-aligned vias, he said.
“Without EUV, scaling beyond the 10nm node will require frequency multiplication,” he said. In that scenario, vendors may have to resort to self-aligned quadruple pattering or directed self-assembly (DSA), he said.
The shift towards the multi-patterning era has some major ramifications for the EDA, photomask and other industries. EDA houses, for example, are readying their multi-patterning tools. But verification costs and optical proximity correction (OPC) run times are expected to soar at the 10nm and 7nm nodes.
“The total run times scales in accordance with the number of patterning steps,” said Yuri Granik, chief scientist within the Design to Silicon Division at Mentor Graphics. “Double patterning alone and SRAFs will increase OPC run times.”
There’s good and bad news for photomask makers and associated tool vendors. In traditional single exposure processing, an IC maker uses one mask. In doubling patterning, an IC maker uses two separate masks to design a device, which boosts production costs. Triple-pattering will require three masks and so on.
In double patterning (two separate mask sets), photomask makers could write the layers in sequential steps with one e-beam tool. In a more likely scenario, a mask maker would simultaneously utilize two e-beams to process each mask to speed up the process.
In multiple patterning, mask makers could see their capital costs soar, as they may end up buying twice as many e-beam tools than before. On a positive note, e-beam makers are seeing robust demand, said Franklin Kalk, executive vice president and chief technology officer at Toppan Photomasks.
The trouble is that e-beams are not keeping up with Moore’s Law. From 2001 to 2005, write times were constant, averaging some 8 hours per mask set, Kalk said. But from 2007 to 2012, the average write times rose to about 10 hours per mask set, he said. “The write times will increase dramatically over the decade,” he said during the panel.
Aki Fujimura, chairman and chief executive of D2S, also painted a sobering picture. E-beam throughputs are increasing by a factor of only one-half, but data volumes are increasing by a factor of two, and mask complexity is jumping by 2x to 5x, he said during the panel.
This week, D2S rolled out one solution to the problem. It introduced TrueMask MDP, a model-based mask data preparation (MB-MDP) technology. Developed to address mask designs at 20nm and beyond, TrueMask MDP reduces e-beam shot count to cut mask write times by 20% to 30%.
Still, there is a crying need for multi-beam mask writers to boost write times. One vendor, Austria-based IMS, has been developing a so-called electron multibeam Mask Exposure Tool (eMET) for the fabrication of leading-edge masks and templates. The company has completed a concept 50keV eMET. Through a programmable aperture plate, the eMET would provide 264,144 programmable beams with 20nm and 10nm beam sizes.
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) has joined IMS’ multibeam mask writer development collaboration. Earlier this year, IMS said Dai Nippon Printing Co. Ltd. (DNP) joined a collaborative effort, backed by Intel and Photronics, to advance IMS’s electron multibeam mask writer tool.
Advantest and Vistec are also developing similar multi-beam tools. It’s unlikely that the multi-beam tools will be ready at 10nm. “They should be ready for 7nm,” Toppan’s Kalk said.
Mark LaPedus has covered the semiconductor industry since 1986, including five years in Asia when he was based in Taiwan. He has held senior editorial positions at Electronic News, EBN and Silicon Strategies. In Asia, he was a contributing writer for Byte Magazine. Most recently, he worked as the semiconductor editor at EE Times.