Published on September 17th, 2012
Third-party data converter IP is designed to ensure that integration into systems-on-chip (SoCs) and IP operation are simple and hassle free. Nevertheless, careless integration of the data converter can lead to poor system performance. This article provides an overview of techniques that help to ensure the successful integration of third-party data converter IP, including proper placement of the data converter macro within the SoC, shielding of analog input, output and reference signals, minimizing the effects of clock jitter and more.
Start with Proper Placement within the SoC
Excessive noise generated in other noisy blocks in the SoC can couple into the data converter block and impact its performance. To ensure the best possible isolation from other blocks, the first step in the physical integration process is to correctly place the data converter macro in the SoC.
First, designers must create distance between active logic (aggressor) and the analog block (victim), as shown in Figure 1.
Figure 1: Placement guidelines applied to an ADC macro
Next, the data converter macro should be placed near the respective analog input/output (I/O) pads to minimize the sources of interference and the parasitic resistance and/or capacitance on the analog signals, taking into account any specific routing requirements such as differential routing or shielding of critical signals.
For applications in which the data converters’ sampling frequency is high (e.g., above 100 MHz), the data converter macro should be placed to ensure that the bond wires are kept as short as possible. Typically this can be achieved if the macro is centered in one of the sides of the die.
Shield the Analog Input, Output and Reference Signals
Any noise or unwanted signals coupling to the ADC input will be seen by the ADC as part of the “true” signal and, therefore, will also be present in its digital output. The smallest voltage that an ADC can distinguish – expressed in least significant bits (LSBs) – establishes the accuracy of the data converter. For a 12-bit ADC, the LSB amplitude can be as small as the LSB amplitude can be as small as ~100 µV.
With such high accuracy requirements, if a switching digital signal (aggressor) capacitive-couples (crosstalk) to the ADC inputs (victim), the spectral content of the coupled aggressor signal, present in digital output signal, can be above the noise floor of the ADC, therefore impacting the system performance (spectral purity).
Likewise, crosstalk to the DAC output impacts system performance in a similar way, i.e., a switching digital signal capacitive-coupled to the DAC outputs can generate spectral content above the noise floor of the DAC.
ADCs with differential inputs, or DACs with differential outputs, have higher immunity to common mode noise because the aggressor is equally coupled to both positive and negative differential signals. To take full advantage of this high noise immunity, the use of these data converters should be accompanied by design techniques such as proper shielding and routing of the external signals.
Similar issues may arise when the data converter requires an external reference. Since the reference establishes the full-scale swing of the data converter, noise or unwanted signals, if coupled to the reference, will also become part of the data converter output word.
Figure 2a shows the frequency spectrum of the output of a 28-nm 12-bit Sigma-Delta IQ-ADC, where coupling between the ADC inputs and a reference signal was present. This leads to excessive power in the second harmonic (h2), effectively degrading the total harmonic distortion (THD) by almost 14 dB. Conversely, Figure 2b shows the performance of the same IQ-ADC after the coupling was removed, resulting in an enhanced THD of -72 dBc.
Keep the Clock Jitter Low
The performance of systems based on data converters, such as communications interfaces, depends on the quality of the sampling clock. The uncertainty of the time instant in which the ADC samples the signal adds to the conversion noise, and thus reduces the converter performance. The uncertainty on the sampling instant is defined as “jitter.”
Clock jitter establishes the maximum theoretical signal-to-noise ratio (SNR) that can be achieved by a data converter using that clock. Figure 3 shows the SNR as a function of the sampling clock jitter, and shows the relationship between SNR, clock jitter and signal frequency (Fin), for the case of intrinsic ADC SNR (SNRADC) of 65 dB.
From this figure it can be concluded that the impact of the sampling clock jitter on the conversion performance (SNR) is not relevant for systems processing low-frequency signals. However, the sampling clock jitter’s impact increases with the frequency of the signals being processed.
Figure 3: SNR degradation due to sampling clock jitter for a data converter with SNRADC = 65 dB
By placing the clock source close to the data converter macro, checking the clock transition times, and minimizing supply domain transitions, SoC designers can account for jitter to ensure that the sampling clock quality is not compromised.
Keep Power and Ground Supplies Clean
Any analog circuit will have a finite power supply rejection ratio (PSRR). Excessive noise injected in the power and ground supplies may affect its performance. This is especially true if it is processing broadband signals, because rejection is typically high for lower frequencies, but naturally reduces at higher frequencies. Therefore, the analog supplies should be clean and proper decoupling used.
Additional effects, such as excessive routing resistance can lead to a direct current (DC) voltage drop outside the data converter operating range. This can also cause a slow alternating current (AC) response to the data converter’s self-generated ripple noise. All these effects can be reduced by proper implementation of supply routing.
For example, when integrating several data converter macros, designers should use dedicated power routing at least up to and including the I/O supply pads. Figure 4a illustrates this requirement for the case of two IQ-ADCs.
For systems with pad number limitations, as long as the data converters use the same clock frequency and phase, multiple macros can share the same I/O supply pad, as shown in Figure 4b. The routing must be kept separate up to the I/O supply pad (in a star connection) and maintain a symmetrical power distribution. Figure 4c illustrates an incorrect implementation of the power distribution. In this example, the power distribution isn’t maintained symmetrically, leading to performance degradation and crosstalk.
Figure 4: Examples of power routing for two IQ-ADC macros. a) Preferred solution, b) solution to minimize pad count, c) incorrect power routing
To ensure successful integration and operation of third-party data converter IP in an SoC, the IP must be designed to take into consideration the application requirements and the harsh nature of the SoC environment. In addition, designers should utilize the previously described implementation techniques. Synopsys makes the SoC integration process simpler by providing intelligently designed data converter IP, and, helps ensure first-time success by offering extensive engineering support, including detailed assembly guidelines, integration checklists and a dedicated integration review by experienced applications engineers.
Synopsys DesignWare Data Converter IP
With more than fifteen years of experience in developing and deploying data conversion IP solutions, Synopsys offers a comprehensive portfolio of over 200 silicon-proven DesignWare® Data Converter IP products including oversampling sigma-delta ADCs, pipeline ADCs, SAR ADCs, and current-steering DACs. DesignWare Data Converter IP products offer very low power dissipation, use a small area, and support process technologies and foundries ranging from 180-nm to 40-nm. For more information, visit www.synopsys.com/IP/AnalogIP/DataConversion.
Manuel Mota, technical marketing manager for data converter IP within the Solutions Group at Synopsys, has worked in the semiconductor industry for more than 10 years as an analog IP designer for Chipidea Microelectronica (Portugal) with responsibility for the design of PLL and data conversion IP cores, as well as complete analog front-ends for communications. He later assumed the role of business developer for data conversion products with the responsibility of product definition and pre-sales technical engagement with customers. He joined Synopsys from MIPS Technologies in May 2009, assuming the technical marketing manager role. Manuel holds a PhD in Electronic Engineering from the Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow. He has authored several technical papers and presented in technical conferences on analog and mixed-signal design.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446
Disneyland Hotel, Anaheim CA. October 6-8, 2015
Santa Clara Convention Center, Santa Clara, CA November 10-12, 2015
Santa Clara Convention Center, Santa Clara, CA Jan 19-21, 2016
DoubleTree, San Jose Feb 29-Mar 3, 2016
San Francisco, CA May 22-27, 2016
Austin, TX June 5-9, 2016