For the past few years, nearly all surveys have identified design debug as one the toughest challenges faced by system-on-chip (SoC) developers. According to data collected by Synopsys from leading SoC, processor, graphics and networking designs, 35 percent of the engineering time and effort for a project typically is spent on debug. SoC debug challenges are further complicated by the addition of advanced testbenches, low power design techniques, analog/mixed-signal blocks and embedded-processors running firmware and/or software. Nevertheless, most design and verification teams continue to use traditional debuggers and debug techniques, simply because intelligent technology is missing from their tool box. Innovation addressing these specific challenges offers a direct means to positively affect the bottom line of design and verification teams, and to some extent tackle the rapidly growing overall cost of verification.
The advent of constrained-random verification and SystemVerilog have given verification teams a way to increase productivity in developing advanced testbenches and hence increase the amount of verification done at both the block and SoC levels. As a result, verification teams are now able to develop more and increasingly larger testbenches. In some of the most recent SoC verification environments, we have seen UVM testbenches that approach a total of one million lines of code. Very often, the testbenches (in number of lines of code) can be as large as 25 percent of the RTL code. As a result, verification engineers have begun to spend more of their time on testbench debug. These testbenches are based on complex and constraint-driven object-oriented code, which requires new constraint and methodology-aware debugging tools for efficient enablement of verification teams. Testbench debug is perhaps the most immediate area where the industry needs to invest and develop technology and solutions.
Protocol debug is another opportunity for significant innovation. Modern SoCs, especially those in the consumer market, leverage several standard interface protocols such as USB 3.0 and MIPI for broader connectivity with other SoCs and systems. Many of these SoCs also require adherence to bus standards (such as AMBA/AXI4/ACE) since they license externally developed CPU architectures within their SoC. In recent years, both the number of protocols on a SoC as well as the complexity of the protocols themselves have significantly increased. For example, USB 3.0 with full-duplex data transfers supporting rates of up to 4.8 Gbps is a significantly more complex protocol to verify than USB 2.0. In order for verification teams to verify and debug a design with USB 3.0, they need to familiarize themselves with the protocol itself, which could mean long learning curves in lieu of time spent developing tests and debug of the SoC. Even once the verification engineer has become sufficiently familiar with the protocol, traditional approaches to protocol debug are extremely tedious and inefficient.
New approaches to protocol debug are needed. These protocol-aware approaches would abstract the deep complexities of the latest protocols away from the verification teams and offer the ability to interact at a transaction level with more than data. Ideally, information about how hand-shakes, complete packets, transfers and transactions are sent and received, and whether protocol violations were triggered, would be provided. Once the root causes of the protocol violations are discovered, these new approaches should transform and link the transaction-level information to the signal-level information for debug of the design itself.
Low power debug is another area for further innovation. It’s well documented that with growth in consumer products and the importance of longer battery life and/or managed heat dissipation, more advanced low power design techniques are being used in almost all SoCs. Design teams now commonly utilize techniques such as power showdown/reset, state retention, low-VDD standby, dynamic voltage/frequency scaling, multi-voltage islands, etc. These advanced techniques require new verification tools and methodology; the always-on functionality of RTL with which verification engineers are familiar behaves differently during power-aware simulations. Traditional debug technology needs new solutions to help verification engineers understand the impact of power intent files on RTL and to aid them in tracing and visualizing the source of power-related errors. For example, an “x” in a power-aware simulation could mean the power to that signal is off, but it could also indicate a bug caused by a structural error, such as missing isolation cells or control sequence errors. Another challenge is to help design and verification engineers understand how power intent (usually captured in external files such as UPF by entirely different power experts) changes the behavior of the RTL blocks they are responsible for coding and verifying. New power-aware debug innovation is needed to address increasingly complex low power verification problems.
The areas highlighted above are only a few cases where further debug innovation is needed. Analog/mixed-signal co-simulation and embedded software bring-up each bring new intricacies and requirements for debug. Furthermore, most of the traditional debug technology is based around technology and methods that increase the productivity of narrowing down the source of design defects or bugs. To take debug technology to the next level of productivity, the industry needs further advancements in bug-finding, bug-prevention and debug automation. These are all areas that have not been addressed historically and that require further investment.
Finally, early bug detection is key to significantly increasing the productivity of the debug process. A bug found and resolved in RTL offers a substantially greater value proposition than that same bug found and resolved at the gate-level. A good example of such bugs would be x-related issues typically found in gate-level simulation – especially in designs with power shutdown/bring up sequences. The ability to catch these x-related issues at the RTL not only saves several iterations through logic synthesis and place and route, but also reduces simulation cycles required due to faster RTL simulation speeds. Finding bugs earlier increases the overall bug finding rate and reduces the cost of verification.
While the industry needs to continue to invest in debug, several key innovations have already begun to appear in the market. Through close R&D collaboration with leading SoC design teams, several key technologies are already in production and addressing the debug of advanced testbenches, complex protocols, low power design techniques, analog/mixed-signal blocks and embedded software. Through these differentiated debug solutions, leading SoC design teams have been able to keep their rising cost of verification in check. However, with today’s SoCs only getting larger and more complex, the industry must continue to boost its focus on debug challenges.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015
Mesa, Arizona March 15-18, 2015
Santa Clara, CA May 6-7, 2015
Encore at the Wynn Las Vegas, NV May 19-22, 2015