Published in Fall 2012 issue of Chip Design Magazine
IC Manufacturing Challenges
Chip Design sat down to discuss future manufacturing challenges with Carlos Mazure, chief technical officer at Soitec; Jeff Hebb, vice president of laser product marketing at Ultratech; Markus Wimplinger, corporate technology development and IP director at EV Group; and Girish Dixit, vice president of the customer integration center and process interactions at Lam Research. What follows are excerpts of that conversation.
Chip Design: Let’s look into the crystal ball and make some predictions. We’ve seen a considerable amount of consolidation in the semiconductor and IC equipment industries. Will the industry continue to consolidate?
Hebb: Every node gets more and more expensive. The industry will continue to consolidate as the nodes shrink. It is going to accelerate. At 14nm, you may see one of the major foundries drop out, or maybe even at 20nm. That’s a strong possibility. In the fabless-foundry world, only the guys with lots of money can afford to design at leading-edge nodes. Building these chip alliances has allowed some of these guys to stay in the game. On the equipment side, it’s the same thing. 450mm will only accelerate the consolidation. There are not going to be that many companies that will go to 450mm. We all know the list. On the equipment side, companies that are really small, or don’t have strong balance sheets, are going to have a tough time funding 450mm. Over time, a lot of the big guys will absorb a lot of the smaller guys—though lately, it’s been more like the big guys absorbing the big guys.
Wimplinger: We’re a mid-size company. Traditionally, we’ve always been early in technology development. That has served us very well in the past 30 years. So we don’t have any plans to be consolidated into another company. But it may be a slightly different story in pure front-end companies, where maybe consolidation is the only way to succeed.
Chip Design: Speaking of the next-generation wafer size, when will 450mm go into mass production?
Hebb: My wild guess for 450mm is 2018. It’s going to take awhile. The Albany consortium, the G450C, will be bringing in alpha tools next year—perhaps the back half of next year. But I think the industry is going to crawl while everyone gets ready and all the 450mm tools get ironed out. So 2018 is not a bad guess. One more quick comment on in-situ metrology and control for 450mm; that’s going to become even more critical at 450mm. Wafer scrap wasn’t tolerated at 300mm. As you can imagine, wafer scrap isn’t going to be tolerated at 450mm.
Wimplinger: For 450mm, we’ll see first production in 2016. For us, scaling our equipment to 450mm is under way. We’ve already announced the first systems available in 450mm. We are leveraging our learning from the 200mm and 300mm wafer progressions. From a technical side, we are not too concerned. But it’s an exercise that consumes R&D dollars. We need to focus our R&D dollars because we have a very wide portfolio of wafer sizes. We serve two-inch in compound semiconductor applications. We have a major share in the antenna circuitry for packaging in MEMS, which are still done at 200mm. And 300mm is not going away anytime soon.
Mazure: It depends on what applications you are looking at. Not all applications will roll out on 450mm. Memories and processors? Yes. But probably not RF and power management. Just to talk 450mm limits the focus. We forget the rest. Many companies are not looking at 450mm, or 14nm and 20nm.
Chip Design: What about stacked 3D chips using TSVs?
Wimplinger: The industry is convinced memory will move to 3D at least for some volumes fairly soon. There will be serious production probably in 2014. The transition to 450mm might be a year or two later. I am convinced the industry will do 3D on 450mm. From our perspective, that’s something a little bit overlooked at the moment in the 450mm discussion. The backend will play a role in 450mm.
Hebb: I agree. The backend packaging isn’t really being considered too much for 450mm. Everyone is focused on the front-end, not backend, for 450mm.
Chip Design: When will foundries move into finFET production?
Hebb: 20nm will come sometime in 2014. When will finFETs come at 14nm? I don’t see that happening before 2016.
Mazure: For finFETs in the foundries, I see risk production at the end or second half of 2015, and then volume production is in 2016. That has to happen before a foundry moves to 450mm.
Chip Design: Are there other issues with finFETs?
Dixit: The scaling path is very clear. You can say finFETs are the next step to scale a device. The challenge for the foundries is how many finFET wafers do they run in their fabs and at what nodes?
Mazure: A processor running at 14nm technology may be of no use if you do not have the Wide I/O or other types of memory that go along with it. So it’s not one part of the industry that must scale. Besides finFETs, everything has to move. Then, if you have the memory and application processor, but you cannot communicate in the system and your RF is not efficient, we still have a problem. Simply put, it’s not just one company pushing the transistor scaling. It doesn’t work that way anymore. The industry has changed in other ways. We are a systems-driven and a customer interface-driven industry. Software is the key.
Chip Design: When will the foundries offer SOI in volumes?
Mazure: Traditional SOI is partially depleted. But that’s a completely different technology than fully depleted. Fully depleted has an SOI structure, but it behaves like bulk. You don’t have partially depleted issues. The interesting thing is that a traditional bulk company like STMicroelectronics is moving towards fully depleted SOI. Now, STMicroelectronics is moving it into a foundry (under a deal with GlobalFoundries). So, it will become an open platform. Today, in a fabless-foundry scheme, there are no finFETs available. That will come.
Mark LaPedus has covered the semiconductor industry since 1986, including five years in Asia when he was based in Taiwan. He has held senior editorial positions at Electronic News, EBN and Silicon Strategies. In Asia, he was a contributing writer for Byte Magazine. Most recently, he worked as the semiconductor editor at EE Times.