Process Control Key to 450mm Wafer Transition Success
Consumer requirements for future mobile platforms are clear: more performance, longer battery life, increased functionality, more memory, lower prices and smaller form factors. To meet these requirements, it is critical that semiconductor manufacturers continue to drive to smaller design rules, creating semiconductors that provide more functionality or memory while allowing the consumer device to be run more efficiently in terms of power consumption. In fact, the semiconductor industry’s continuous drive to increase performance and decrease costs has been critical to the growth of the consumer electronics and semiconductor industry. The problem is that while there is a technical path to success, it is becoming increasingly more expensive to manufacture semiconductor devices at these smaller design rules.
For example at design rules below 22nm, semiconductor manufacturers are planning to implement advanced lithography techniques (double patterning, EUV), new, exotic process materials and complex transistor designs (3D FinFET) that will require an increasingly higher investment in capital equipment and higher manufacturing costs. To counter exponential rises in manufacturing costs while meeting consumers’ increasing demand for smaller, faster and cheaper devices, chipmakers are growing more focused on the wafer size transition from 300mm to 450mm.
The transition to 450mm wafers helps combat the rising costs of manufacturing next-generation design nodes by increasing the number of potential semiconductor die per processed wafer and theoretically requiring a lower number of 450mm processed wafers to meet demand. A chipmaker yielding die at a similar or higher rate on 450mm wafers than they did at 300mm will reap the benefits of increased manufacturing productivity, reduced energy and water usage and lower overall costs. However, it is important to understand that these benefits are not realized unless the chipmakers can deliver high die yields. Lower than expected yields creates an amplified cost penalty for chipmakers, as they must digest the costs of the lost product while having to process more wafers through their production lines in order to meet demand.
Due to the increased value of a 450mm wafer (more die per wafer) and extremely high investment needed in a wafer size transition (R&D, new fabs, new equipment), getting to high yields as fast as possible will be paramount to success. As a result process control (defect inspection and metrology) will play a critical role in helping the industry successfully navigate this transition. Expected higher investments in process control will provide the entire industry with a high return on their investment by helping:
- Reticle manufacturers provide defect free photomasks
- Wafer manufacturers develop defect free and extremely flat wafer substrates
- Process equipment manufacturers develop tools that reduce yield inhibiting defects, and provide precise performance with very low variation and high uniformity across the wafer
- Chipmakers quickly develop processes and process modules that stay within increasingly smaller process windows, are highly repeatable and produce a low defect density. In addition to quickly developing high yield processes, the processes will also require continuous monitoring to identify and reduce the impact that process excursions have on yield.
For chipmakers, it is expected that yielding die on 450mm wafers will come with significant challenges and a steep learning curve. In addition to the increasing challenges in yielding devices with smaller design rules, the transition to a larger design rule brings additional yield challenges. Increased chip density, new, immature process tools, tighter process windows, center-to-edge process variations and wafer edge defects all present significant challenges to obtaining the necessary yields for success. Industry focus will be heavily centered on ensuring a fast yield ramp with particular emphasis on edge-die defectivity and quickly understanding their variation windows for each process.
Defect inspection and metrology tools are critical components to ensure success in all of these areas. Having these tools available during early development and ramp will help make this a more cost effective transition. We at KLA-Tencor introduced our latest generation bare wafer Surfscan inspection platform at SEMICON West with 300mm and 450mm capability to address parallel development for smaller design rules as well as the wafer transition. This is an important first step in helping the industry develop cleaner 450mm wafers and processing equipment and KLA-Tencor is closely collaborating with industry consortiums, equipment manufacturers, wafer manufacturers and chipmakers to promote a smooth transition to 450mm. Without it, future generations of smartphones, tablets or the next “great” consumer device may become a lot more expensive.
As Senior Director of the Global Customer Group at KLA-Tencor, Robert Cappel works with customers to understand their current and future requirements, while aiding KLA-Tencor in delivering solutions to meet those requirements.
Cappel has 26 years of experience in the semiconductor industry with an emphasis on process control. During his first 10 years in the industry, he worked in process engineering and yield management roles at Dupont Tau Labs and Digital Equipment Corporation. At KLA-Tencor, he has worked in both technical and strategic marketing roles in the optical and e-beam inspection groups. Cappel’s interest in semiconductor technologies grew while he was completing his Bachelor of Science degree in Imaging Science at Rochester Institute of Technology.
The author of 14 technical papers, Cappel has written about yield management techniques, e-beam inspection applications and the value of yield management. He has also presented on yield management strategies at conferences including Institute of Electrical and Electronics Engineers (IEEE), the International Symposium on Semiconductor Manufacturing (ISSM), and KLA-Tencor’s Yield Management Seminars.