Published on January 31st, 2013
Two notable changes have occurred in the semiconductor market in recent years. First, thanks to increasing vertical integration and a move up the value chain, at least the lower levels of the software stack have become the responsibility of the semiconductor companies. Secondly, power consumption has become a major concern for vertical markets outside the traditional driving market of mobile devices. One consequence of these changes is the increasing pressure to extend power-aware design to the system level, where decisions can have a far greater impact on power consumption.
For mobile devices, the chief concern has been energy consumption, which governs battery life. However, in all devices -- from mobile to the network infrastructure and servers powering the cloud -- increased performance has led to power density concerns. In consumer equipment, high power density directly leads to higher unit cost in the form of chip packages, heatsinks, and fans. In servers, higher power density leads directly to more air conditioning, a major component in a data center’s daily running cost.
Semiconductor companies are now using more flexible parallel, multi-processing architectures that can meet maximum performance demands without excessive power density. Designers combine these architectures with advanced low power design techniques such as power shut-off (power gating), multi-supply voltage (voltage islands), and dynamic voltage and frequency scaling (DVFS) to control both power density and energy consumption. These advanced techniques have plenty of ramifications for the chip design, implementation and verification flows. And for the Electronic System Level (ESL) designer, they introduce two new challenges.
First, the decision to apply any of these techniques is an architectural decision taken early in the design flow. However, the ability to accurately measure the results of those decisions is poor early in the flow, and accuracy improves greatly as the design is refined. Today, power estimation with sufficient accuracy to give the designer confidence that the SoC will indeed meet its power specification is only available from the register transfer level (RTL) stage, by which time the architectural design decisions are already fixed. This is illustrated in figure 1. So on what basis does a designer know the architectural decisions are going to enable the power specification to be met?
|Figure 1: Effect on power versus measurement accuracy|
Figure 2 illustrates a typical Android system. The drivers are under the Linux kernel whereas the power management API would be one of the available libraries.
|Figure 2: Typical Android device|
These challenges have increased interest in power-aware design at the system level. Some have even suggested that standards are necessary to define ESL power modeling – for example, the Silicon Integration Initiative (Si2) has proposed a concept of atomic power models for ESL. So what can be reasonably done to extend power-aware design to the system level? I offer some guidelines based my personal opinions below:
System-level power models are not “one size fits all”
ESL is not a single level -- it covers a range abstraction levels. This would greatly affect the power or energy accuracy expectation. For some early architectural decisions, and to optimize application software, relative accuracy (correct ranking of alternatives for power consumption) may be sufficient versus absolute accuracy. It may not even be necessary to fully or even partially model the block’s function.
Modeling is also interdependent with the execution tool’s model of computation. The combination needs to correctly simulate the common low-power techniques. SystemC TLM-AT (approximately-timed transaction-level models) with TLM2 interfaces may be the best compromise. Furthermore, efforts in this area should not re-invent the wheel on model infrastructure but instead fit with existing frameworks like IP-XACT. The modeling framework should also cover the board-level components and interfaces, including analog, RF and power management, if it is under the control of the SoC and software.
Models alone are not very useful without activity
Accurately measuring block activity in system modes of interest is essential for power estimation. At RTL, a switching activity format is now defined as part of the IEEE-1801 standard. It would seem to be low-hanging fruit to extend this for TLM2.
Need ESL-compatible descriptions for power domains, their states and the system modes
Existing format standards such as Si2’s Common Power Format (CPF) or IEEE-1801 should need little modification here, but one issue would be the need to define corruption semantics for TLM. These are necessary to satisfactorily model the off-state in power shut-off, in order to confirm correct software control of the power architecture.
In conclusion, there is a clear need for power-aware design to move to the system level, but there are different requirements for different purposes, and many alternatives to meet those requirements. The move to ESL low-power design is just starting, and rather than depending on standards to enable the move, the system level techniques and power models should be left to mature. Standardization can follow to enable mainstream use of the design and modeling techniques that are proven to work.
Pete Hardee joined Cadence Design Systems in early 2010 as director of solutions marketing, responsible for the low-power solution. He has eighteen years experience in the EDA and Silicon IP industries. Hardee’s experience previous to Cadence includes various engineering, management and executive positions in applications, marketing and sales at Synopsys, CoWare and Silistix. His areas of technical expertise include low power design and verification, high-level synthesis, interconnect IP and ESL technologies. While at CoWare, Hardee was instrumental in founding the Open SystemC Initiative, serving as its inaugural co-chair, and executive director. He has a BSc (Eng) degree in Electrical Engineering from Imperial College, London, and an MBA from Warwick Business School.