Tomorrow’s Semiconductor IP – Not Business as Usual
The semiconductor IP market is forecasted to grow from $2B to $3B by 2016 according to research firm Gartner. That’s adding about a $1B from today’s market size. Stated another way, the market will increase by 50 percent over the next few years. What’s driving this explosive growth? As an IP vendor with a broad portfolio, Synopsys works with many customers and is in a good position to answer the question. The answer is simple: it’s the continuous drive to integrate more functionality onto SoCs combined with aggressive schedules that require more outsourcing of IP.
But how do you define SoC? The standard definition, of course, is system-on-a-chip, but some might very well define it as software-on-a -chip or server-on-a-chip. In fact, all three types of SoCs are driving the IP market now and will continue to drive it for the next several years.
|Figure 1: Gartner forecasts semiconductor IP market to grow to $3B by 2016|
It is not uncommon for today’s system-on-chips to have 50 million instances, particularly in high-end applications processors, which are at the heart of today’s tablets and smartphones. These devices integrate multiple CPUs, GPUs, audio and video subsystems, and as many as 60 other functional blocks. Of course, they face intense time-to-market pressure and require substantial innovation to manage the power. The engineers working on these types of chips must move at lightspeed and quickly determine how to meet their aggressive project schedule without compromising quality. The solution for many is to use third-party IP for common functions such as USB, PCI Express® and DDR. The increasing shift from make to buy is clear. The amount of outsourcing of IP functions has risen significantly over the last few years. Gartner predicted that the average outsourcing of functions on a chip will increase from 20 percent to 40 percent from 2009 through 2014 (see Figure 2). Synopsys is right on track with data showing an increase of 10 percent over the last three years. Consumer-driven devices like tablets and smartphones are leading the charge with the highest percentage of outsourcing because they are under such intense time-to-market pressures.
|Figure 2: Gartner predicts third-party IP usage to double, driving market growth|
The next big challenge in system-on-a-chip design will be effectively implementing these chips in advanced technologies such as 20-nanometer (nm) planar and FinFET processes. These technologies promise the continued advance of Moore’s Law but also make the implementation of SoCs more complex. For example, it’s not unusual to have more than 2000 restrictive design rules (RDRs) affecting the layout. The number of timing corners for signoff has escalated as well. For 20-nm designs, Synopsys is seeing requirements for more than eight times the number of process, voltage and temperature (PVT) points compared to a 65-nm design. And add to that, double patterning and preferred orientations which make place-and-route implementation much more complicated.
|Figure 3: More companies are looking to third-party IP to help mitigate the increasing SoC complexity associated with 20-nm planar FET and FinFET architectures|
In addition to the physical challenges, functional challenges abound as well. To illustrate, consider a “simple” function – a USB interface. Did you know that there are more than 3000 pages in the USB specifications? As a result, USB 3.0 verification has gone up by a factor of about 20 compared to USB 2.0. With required support for 5V tolerance, implementing USB PHYs in these advanced nodes is not trivial either. The verification and implementation challenges will continue to grow as USB evolves. Furthermore, the USB Promoter Group recently announced the next generation of USB – the 10G SuperSpeed USB supplement to the existing USB 3.0 specification – which delivers twice the data speed of current connections. So much for a “simple” function.
However, just because a function is difficult doesn’t mean it is differentiating. The right solution in many Synopsys customers’ minds is to outsource it. Dr. Seh-Woong Jeong, executive vice president for System LSI at Samsung put it best in an article published for the Synopsys Journal when he said, “Our make-versus-buy policy for IP is simple—in theory. If we need standards-based IP such as USB or PCI Express, the team will turn to trusted outside suppliers for the blocks…If our analysis suggests that the SoC project timescale won’t allow us to create a particularly complex IP block and differentiate it in time to meet a product launch window, we will, again, use existing IP from a trusted third-party vendor in order to meet our time-to-market requirements.”
The Rise of Subsystems
There is no doubt that outsourcing is critical for system-on-chips but it also impacts the second type of SoC – software-on-a-chip. With 35 percent to 50 percent of the budget for a typical SoC allocated to software, designers are increasingly turning to outsourcing to address these requirements. This represents an important inflection point in the semiconductor IP market. As both hardware and software complexity increases, customers are asking Synopsys for more advanced, integrated solutions, which we call subsystems.
What is a subsystem? It is the hardware, software and prototyping environment that delivers a complete, complex function that is ready to integrate into an SoC. Synopsys’ first subsystem is an audio-based subsystem that integrates an optimized 32-bit ARC™ audio processor with standard interfaces such as S/PDIF and I2S. The most interest in the subsystem has been generated by the software that’s included. Using the industry standard GStreamer media streaming interface, the entire subsystem looks like a simple audio plug-in to the host processor. The audio subsystem also includes both virtual and FPGA-based prototypes to accelerate software development and validation of the full system (see Figure 4).This type of subsystem, which addresses both system-on-a-chip and the software-on-a-chip challenges, will continue to gain traction as the semiconductor IP industry grows and evolves.
|Figure 4: The DesignWare® SoundWave Audio Subsystem addresses both system-on-a-chip and the software-on-a-chip challenges|
In the Cloud
Not only are designs getting more complex and requiring more hardware and software integration, but everything is moving to the cloud which puts tremendous demands on the data center to reduce space, cost and power. According to a recent New York Times article, data centers worldwide use about 30 billion watts of electricity, roughly equivalent to the output of 30 nuclear power plants. A single datacenter can draw as much power as a medium-sized town. The industry’s answer to this problem (or opportunity) is a new type of chip called a microserver or a low-power server (see Figure 5).
Figure 5: 64b ARM® v8 CPU with optimized IP integration reduces power in data center microservers
These chips are literally servers-on-chips, integrating common functions such as Ethernet, SATA, PCI Express, memory controllers and fabric switches along with the traditional CPU and cache memory.
Microservers have the ability to significantly reduce power through integration particularly for such common tasks as web servers, search engines, on-line transactions, and video-on-demand. Synopsys believes that innovation in low-power servers will create opportunities for IP vendors and be one of the drivers of growth in the overall IP market over the next few years.
System-on-a-chip, software-on-a-chip, server-on-a-chip – whatever SoC means to you – certain trends are clear. The tremendous, continued drive for integration combined with aggressive schedules will require more outsourcing of IP, growing the market by 50 percent over the next few years. The IP of tomorrow will be nothing like the IP of today. It will require a fundamental shift in methodology, architecture and how we go about designing IP. IP vendors need to be on the leading edge of technology as well as on the leading edge of integration, including software integration, to continue to provide value to the semiconductor industry – for the IP industry, it’s no longer business as usual.
John Koeter, Vice President of Marketing, Solutions Group, Synopsys
John Koeter joined Synopsys in 1998 and is currently Vice President of Marketing for the Solutions Group. In that capacity, he is responsible for the marketing of Synopsys' DesignWare® intellectual property (IP), Professional Services and System-Level Design products. Before coming to Synopsys, Mr. Koeter held marketing, engineering, and corporate application engineering positions with Texas Instruments and Advanced Micro Devices. Mr. Koeter holds a BSEE degree from Cornell University.