Mitigating RFID/NFC Cost & Power Challenges

Introduction
The market demand for radio frequency identification/near field communication (RFID/NFC) tags is growing rapidly and is expected to continue for the next decade. IDTechEx forecasts that the number of passive RFID tags will increase from just under 3 billion units in 2011 to almost 250 billion units in 2021 (IDTechEx, 2011). The unit growth will be driven by a wide range of applications, including logistics tracking, government issued identification cards, and pharmaceutical tagging. As the NFC ecosystem grows and more mobile devices are NFC enabled, the market will expand further. Companies are already starting to develop and market programmable NFC tags that can be used to control smartphones or tablets just by placing the mobile device in close proximity to the tag (e.g., Samsung’s Techtile).

Currently the RFID tag market is dominated by a few large suppliers, but with the emergence of localized applications, more new companies enter the RFID space. For these new entrants, the key to success is to develop an RFID/NFC tag with cost and power consumption performance on par with industry leaders. Access to expertise in embedded multiple time programmable non-volatile memory (MTP NVM) is one of the competitive barriers that new tag suppliers need to overcome to deliver a competitive product.

MTP NVM is required to implement the common RFID and NFC standards. Almost all leading RFID/NFC tag IC suppliers employ internal MTP NVM development teams to create their own optimized solutions. However, for new RFID/NFC players, developing embedded MTP NVM requires more cost, expertise, and time than their internal resources allow, so they often outsource the MTP NVM development to a third party. This article will examine the advantages of using a third-party MTP NVM supplier, the cost and power standards that are required to compete with the industry leaders, and key evaluation criteria for selecting third-party MTP NVM suppliers.

Reducing the cost per RFID/NVM tag
With tag IC volumes expected to increase ~100x from 2011 to 2021 (IDTechEx, 2011), minimizing the cost per tag is critical. There are three major components to the cost of an RFID/NFC tag: die area, wafer processing, and test costs.

MTP NVM die costs
The overall die area depends on several factors, but the number of MTP NVM bits is critical. Using publicly available information on leading RFID tags, the total die area for a tag including 128 bits or 256 bits of embedded MTP NVM is less than 0.25mm2 with the MTP NVM occupying 25 to 40 percent of the overall area. For price-competitive tag ICs, the third-party MTP NVM block should support 256 bits in approximately 0.05mm2. By limiting the MTP NVM IP to 20 percent of the overall target area, tag IC designers are enabled to develop a solution that may be lower in overall area and cost than some of the leading tag ICs on the market today. The compact area of the MTP NVM block also allows the number of bits available for end customer use to be expanded to 512 bits or 1,024 bits while remaining cost-competitive.

Companies with internal MTP NVM development have the advantage of optimizing the MTP NVM for their specific design. Optimization may include a custom layout or a re-use of existing blocks, such as a bias current generator or oscillator that already exists in the tag IC. New RFID/NFC developers can mitigate established players’ internal-team advantages by choosing an experienced third-party supplier. An IP supplier that understands the market will be able to design an MTP NVM block that will work across a broad range of existing bias currents and oscillator frequencies. Fortunately, it is very common for an RFID/NFC tag to have an internal oscillator frequency of 1.92MHz, making it easier for a third-party IP developer to address a majority of the market.

Wafer processing costs
The second component of the overall IC cost is the wafer processing. Today, and for the foreseeable future, the sweet spot for RFID/NFC tags appears to be 180 nanometer (nm), or the associated optical shrinks. The 180-nm process offers excellent analog and RF performance and most foundries have accurate models to reduce risk in design. Because there is only a relatively small digital component to the tag IC, the 180-nm process provides adequate density and performance for the digital circuits.

Foundries’ 180-nm process nodes range from very similar to completely GDS compatible, which gives IC vendors the option of using multiple manufacturing sources without having to modify or retune the design. Having multiple manufacturing options helps to keep the wafer costs low. Third-party MTP NVM vendors are generally foundry independent and are able to offer similar or identical IP blocks at multiple foundries. This foundry flexibility allows RFID/NFC tag IC developers to leverage a multi-foundry manufacturing strategy.

Production test costs
The final cost component is the testing required during production. Silicon testing can be a significant factor in the overall tag IC cost and the MTP NVM can be a major contributor to the test time. There are two components of MTP NVM testing that are most commonly cited as being the most expensive / least desirable by customers: retention bake and array programming. During the retention bake, the wafers are baked unbiased at an elevated temperature (250°C) for a period of time (24 hours) to guarantee that the data retention will achieve the target specification (typically 10 years at 85°C or 125°C). The array programming confirms that not only are all the support circuits, such as the digital controller and the charge pump, working properly, but it confirms that all of the bits in the array can be successfully programmed to both a logic “1” and a logic “0” state. Point defects in the process can create a bit that is stuck in either a “1” or a “0” state.

Tag IC developers should work closely with third-party suppliers to optimize both the retention bake and the array programming contributions to the overall test cost. They should ask the MTP NVM supplier for a temperature acceleration factor for the data retention bake that is based on silicon data. The acceleration factor allows the tag IC vendor to modify or reduce either the bake time or temperature to minimize the cost without sacrificing test coverage. Third-party suppliers should have implemented various test modes into the MTP NVM block to reduce the time required to validate the array. With a properly designed test flow and test mode access, the test time required to validate the function of the entire array can be reduced by 10x or more.

Minimizing RFID/NFC Power Consumption
In addition to reducing costs, minimizing power consumption is critical to success. Both programming power and read power can adversely impact a design’s overall power consumption; conversely, in skilled hands, they can be reduced to the point that they can become a competitive advantage.

Programming power
For an RFID or NFC tag, the programming power of the MTP NVM relates directly to the write sensitivity specification for the system. Industry leading tag ICs quote write sensitivity down to -16dBm. This equates to a total available power at the tag of 25uW. Within the 25uW, the tag IC must account for losses in the antenna and rectifier circuits, as well as operate all the other circuitry on the tag. MTP NVM consumes a majority of the active power during a program operation, so a reasonable target is 10uW or less of continuous programming power. When operating off of a 1.6V-1.8V supply, as is common for 180-nm processes, the average programming current is limited to 5-6uA or less. Because the programming operation typically requires a high voltage of 9-11V, creating a charge pump circuit that will generate 9-11V from a 1.8V supply and use less than 5uA is challenging.

However, the average current is not the only criterion for write sensitivity. The peak current is also important. Because the MTP NVM requires a high voltage to program, there is an initial spike of current when the charge pump starts up. This spike can be much greater than the average current and will likely exceed the available power budget. To supply the peak current, the RFID or NFC tag will need to have on-chip capacitance to store the energy needed for the initial surge. Because the ICs are so small and the space available for on-chip capacitance is similarly small, the peak current needs to be minimized as well.

Developing MTP NVM with low programming power consumption involves a delicate balance among a variety of factors including programming speed, charge pump area, and programming algorithm. Being too conservative will result in an MTP NVM block with a prohibitively large area or high power consumption. Being too aggressive may result in an MTP NVM block that performs well under typical conditions but fails to meet the target performance when variations in processing, supply voltage, and temperature are introduced. Developers should make sure the third-party MTP NVM supplier has made the appropriate design tradeoffs to optimize performance and has performed silicon testing to demonstrate the performance and power consumption.

Figure 1 shows silicon results for both the peak programming current (in this case ~8uA) and the average programming current (~4uA) for an MTP NVM block. Peak programming current spikes can be double the average current consumption and RFID/NFC tags must support both the average current consumption over the programming event as well as the peak programming current that occurs for only a very short timeframe (a few microseconds). Failure to account for both current profiles can result in an un-usable RFID/NFC tag IC.

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Figure 1 : For programming operations, the RFID/NFC tag must account for both the initial peak current as well as the average current consumption.

Read power
Analogous to the programming power impacting write sensitivity, the read power impacts the read sensitivity. Leading RFID/NFC tag ICs specify a read sensitivity of -20dBm, which equates to 10uW of read power. Because the read operation of an MTP NVM should not require a high voltage, the read operation consumes much less power. In addition to eliminating the need for the charge pump and other high voltage / high current circuitry, the read operation will often be performed at a reduced supply voltage. For the most power sensitive applications, 1.0V or lower is a common read voltage.

Read current usually varies linearly with read frequency. For applications that must read at 1MHz or greater, it is not unusual to have read currents of 2-3uA. For a typical 160kHz RFID/NFC tag IC read frequency, the total read current can be reduced to <500nA per read operation. With a 1.0V supply, the read power is 0.5uW or less. Figure 2 shows silicon results of read current versus read frequency for an MTP NVM block.

Optimizing the read operation will also vary based on the application needs. Reading a single data bit at a time will provide the lowest overall read current and the best read sensitivity. This is the right solution when the data stored in the MTP NVM is going to be delivered to the RFID reader across the RF interface a single bit at a time. Many basic RFID tags operate in this manner.

If, however, the data stored in the MTP NVM array needs to be used in larger blocks—for example, when RFID/NFC tags are integrated with additional functionality like  temperature sensing—the data in the MTP NVM array may be used for performance trimming or calibration and 16 bits may be needed at once. In this case, the key parameter is the amount of power required to read 16 bits in a given period of time.

In general, the power required to read 16 bits is not 16x the power required to read a single bit if the design has been done efficiently. A more reasonable estimate is that a 16-bit read will take 4-6x the power of a single bit read. Reading a single bit at a time must have an access time that is 16x faster than that of a 16-bit read to output the same number of bits in a given time. Because read power scales with read frequency, the slower read frequency (16x lower) of the 16-bit read easily offsets the higher read current (4-6x higher) and can result in 2.5x – 4x lower overall power consumption relative to a single bit read.

Similar to the programming power consumption specification, working with silicon-proven third-party MTP NVM IP increases the confidence in an optimal design solution across all of the manufacturing and application environmental variables.

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Figure 2 : Controlling read frequency is critical to controlling read power consumption

Advantages of using third-party MTP NVM IP
Although the current RFID/NFC tag market leaders all have internal MTP NVM development teams, emerging entrants in the market can benefit from three key advantages by  using  third-party MTP NVM IP.

Time to market
While MTP NVM does not have a formal standard like the USB, HDMI, and DDR interfaces, RFID/NFC tag performance requirements are consistent enough to create a de facto standard. Using this de facto standard, third-party MTP NVM suppliers can develop a family of standard products that meets the needs of a majority of the market. With the immediate availability of proven MTP NVM blocks, RFID/NFC tag IC developers can reduce their overall time to market.

Upfront development costs
Developing an MTP NVM block that is both compact and reliable can take an experienced team multiple years to fully develop and qualify. It is not uncommon for embedded flash development costs on a new process node to exceed $10 million. MTP NVM used in RFID/NFC tags can be developed for less, but assuming less than $2 million to develop a new MTP NVM block is likely to be optimistic. Licensing from a third party can reduce the upfront cost by approximately an order of magnitude. Third-party MTP NVM providers are able to amortize the development costs across many customers and can leverage past experience to reduce the overall development cost.

Ongoing support costs
Once the MTP NVM has been developed and qualified, there will be an ongoing support requirement as it is integrated into the RFID/NFC tag ICs. Maintaining a technical team to provide support for everything from layout integration through production test and yield enhancement can be costly. Similar to the upfront development costs, a third-party IP vendor is able to spread the costs of maintaining a team of experts across a broader customer base.

Keys to selecting a third-party MTP NVM supplier
When choosing a third-party supplier, RFID/NFC designers must consider the supplier’s experience, silicon testing methodology, and support infrastructure.

Experience developing MTP NVM on multiple process nodes, across multiple foundries, and for applications outside of RFID/NFC tags provides the baseline for providing a high-performance, low-risk MTP NVM block. Failure to work with an experienced supplier is much more likely to result in additional project delays and costs as the MTP NVM supplier develops the institutional knowledge that comes with experience.

Second, because RFID/NFC tags have such specific area and power consumption demands, confidence in the third-party MTP NVM performance can be gained only through stringent silicon testing. A good characterization testing methodology will involve testing all of the key specification parameters across process skew lots, temperature, and voltage. Qualification testing should meet the requirements of one or more of the applicable industry standards that require endurance and retention testing from a minimum of three manufacturing lots.

Last, a dedicated support infrastructure can help when the inevitable questions on integration, production test, yield enhancement, and other topics arise. Working with a third-party supplier that has a dedicated technical support team responsible for MTP NVM customers will allow any questions or issues to be answered and addressed before they impact the end product release.

Conclusion
The rapid increase in the use of RFID/NFC tag ICs is enticing a large number of new companies to enter the market, but competing with established suppliers is a challenge. The current market leaders have a head start because they already have internal MTP NVM development teams. They also already have embedded MTP NVM blocks, which are one of the key components of RFID/NFC tag ICs. The time-to-market and development costs to build an MTP NVM block are significant. By selecting an experienced third-party IP supplier and a proven MTP NVM block, newcomers to the market can accelerate their development cycle.

The Synopsys DesignWare® AEON® family of NVM IP is a good example of proven IP. It has been designed to deliver detailed, silicon-based performance data on endurance, retention and write disturb. Each DesignWare AEON IP product is architected to optimize performance for particular applications, whether it’s real-time data logging, high precision trimming, ultra-low power wireless or customer preferenc settings. For more information on Synopsys’ DesignWare AEON NVM IP solutions, visit http://www.synopsys.com/IP/SRAMandLibraries/Pages/AeonNoveaNvm.aspx.

Craig Zajac is the Senior Product Marketing Manager for the non-volatile memory IP product line at Synopsys. Prior to joining Synopsys, Craig managed the non-volatile memory portfolio at Impinj and Virage Logic. Craig has over 10 years of experience in the semiconductor industry and has held product marketing and engineering roles at companies including National Semiconductor, ON Semiconductor, and Motorola. Craig holds a BS and MSEE from Stanford University and an MBA from Arizona State University.


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