Today’s smart phones and mobile devices are for more than just voice and data. They are more powerful than desktop computers that were state-of-the-art just a few years ago. Additionally, user interface on mobile devices is simpler than desktop computers due to the mobile devices' ability to be “aware” of their environment—gathering and analyzing information about position, acceleration, temperature, touch, light, pressure, flow, and so on—to determine the user's actions and intentions and then act on that information.
Mobile devices must demonstrate some level of environmental awareness to optimize functionality. Sensors are typically used for this purpose as they translate real-world environmental quantities, like motion, touch, or acceleration into data that are suitable for electronic handling. To complete this process, the electronic system must acquire the information, convert it to an electrical quantity, and process it, which typically occurs through digital signal processing. As illustrated in Figure 1, a typical mobile system’s sensor signal processing chain includes the sensor itself and its control or biasing circuitry, the analog signal conditioning circuits, an analog-to-digital converter (ADC) and a digital signal processor.
|Figure 1: Typical signal processing chain for mobile applications|
Integrating sensor data acquisition in mobile applications
Mobile applications lead the system-on-chip (SoC) integration trend due to their challenging area and power constrains. Effective sensor data acquisition system designers can take advantage of this trend to further reduce costs and save power. Today’s system integrator can choose from a wide range of data converter IP created specifically for integration with digital processing blocks for sensor-based applications. They offer a range of performance and functionality that matches the characteristics of most sensors.
When implementing a sensors-based system for mobile applications, alternative system partitions may be used. Integrating the ADC with the application processor is an effective solution in systems using discrete sensors due to the cost reduction.
Alternatively, a dedicated SoC with an embedded sensor can also be an effective system solution. For example, micro-electro-mechanical systems (MEMS)-based sensors can be embedded with the corresponding digital signal processing block, thus integrating the complete chain in a single die. Regardless of the implementation choice, the data converter is integrated with the digital signal processing block in a single chip.
Advantages of integrating data converters with digital processors
It is important to understand the pros and cons of integrating an ADC into a signal processor. Compared to using a discrete ADC chip, integrating an ADC in a digital SoC has several advantages, all of which are important for space-sensitive mobile applications. Integrating the ADC simplifies the system design, reduces the bill of materials (BOM), and minimizes the hardware footprint. In addition, integrating the ADC can reduce system power consumption and improve performance.
Integrating the data converter with the digital processor reduces total system power, which is critical for mobile devices with limited battery life. This is achieved by eliminating the need for additional interface blocks to communicate between the separate chips. Power consumption can be further reduced by using more efficient power management options. For example, designers can use SoC power management techniques such as turning off individual power supplies for unused blocks, with the ability to quickly restore the previous state (by storing calibration data while in power-down mode). Another power management technique enables different sleep modes where the block is powered-up only when activity is detected on the sensor.
Furthermore, typical non-integrated devices require high (for example, 5V) supply levels, whereas most integrated circuits are supplied at 2.5V or lower. Therefore, incorporating fewer non-integrated devices in the system, through additional system integration, can reduce the number of supply levels required for system operation and thus reduce the total system power dissipation and cost.
Performance improvement and noise considerations
Integrated and discrete components differ in how the system environment impacts their performance. Designers need to understand the potential implications of a noisy SoC environment in the performance of the converter as well as how to manage them.
An embedded data converter can be affected by noise coupling from on-chip digital signal processing blocks. Digital signal processing blocks are typically core limited (i.e., the total silicon area of the chip is determined by the internal circuitry), so any additional circuitry that could be introduced to improve the noise isolation of the data converter would increase the silicon area used in the chip and the total mask cost. Because of this cost penalty, designers generally choose to not add circuitry and instead rely on architectural techniques at the ADC and system level to achieve the required noise immunity.
A 12-bit converter has to resolve signal amplitudes down to a least significant bit (LSB) of 730uV. This sensitivity makes immunity to noise a key performance criterion for integrated data converters. Inside a digital integrated circuit, supply noise, and even substrate noise, can easily surpass the 730uV amplitude and disrupt the operation of the data converter. If this occurs, mobile systems that use a data converter can deliver erroneous information. For example, designs incorporating accelerometer acquisition chains could report incorrect information about the position and orientation (tilt) of the device.
Designers can address noise isolation issues at several levels:
Today’s mobile devices depend on environmental awareness to optimize their functionality. Sensors are the elements that translate real-world environmental quantities into electric characteristics suitable for electronic handling. The data converter is an essential element of the data acquisition chain which is typically integrated with the digital signal processing block in a single chip. When compared with using an additional discrete ADC chip, the integration option greatly simplifies the system while reducing the BOM and footprint costs. In addition, integrating the ADC also reduces system power consumption and improves performance, yielding a more efficient system.
With more than 15 years of experience in developing analog IP solutions, Synopsys offers a comprehensive portfolio of more than 100 silicon-proven DesignWare® Data Converter IP products consisting of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), auxiliary converters and analog front-ends (AFEs). Synopsys’ strong application expertise in areas such as broadband wireless communications (i.e., LTE/WiMAX, WiFi802.11n, WiFi-ac), wireline communications (i.e.,G.hn, MoCA) IF demodulation, video, imaging and multimedia enables us to deliver high-quality data converter IP that help customers meet the specific design requirements for their target applications. The DesignWare Data Converter IP products offer very high performance, high speed, ultra low power dissipation, small area and support a wide range of foundry process technologies ranging from 180-nm to 28-nm. For more information, visit www.synopsys.com/IP/AnalogIP/DataConversion .
Manuel Mota, Technical Marketing Manager for Analog IP within the Solutions Group at Synopsys, has worked in the semiconductor industry for more than 10 years as analog IP designer for Chipidea Microelectronica (Portugal) with responsibility for the design of PLL and Data Conversion IP cores as well as complete Analog Front-Ends for communications. He later assumed the role of Business Developer for Data Conversion and Audio products with the responsibility of product definition and pre-sales technical engagement with customers. He joined Synopsys from MIPS Technologies in May 2009, assuming the Technical Marketing Manager role.
Manuel holds a PhD in Electronic Engineering from the Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow. He has authored several technical papers and presented in technical conferences on analog and mixed signal design.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
San Francisco, CA December 13-17, 2014
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015
Mesa, Arizona March 15-18, 2015
Encore at the Wynn Las Vegas, NV May 19-22, 2015