Published on June 11th, 2013

Quest for the 10K Chip: Enter Yotta Data Sciences.

Pundits and providers in the chip design world are pretty much agreed that the combination of higher abstraction, design services and lower-cost tools has almost brought the cost of designing a chip to acceptable levels.  They are also agreed that the use of the cloud will be of limited help and NRE will remain a large and growing cost center. (see video interview series at www.newtechpress.net)

They all may be wrong on that last point.

Yotta Data Sciences is a tiny, two-person company taking on a huge challenge -- how to virtually eliminate the cost of NRE through data interpretation...in the cloud.

The company has developed a technology and methodology that assigns “smart signatures” throughout the data that identify when the IP has been created, who created it, who has modified it and who has permission to use it, among other information points.  That not only protects the data (and can help determine if the IP has been stolen) but it can identify which licensee a change will affect, and alert only those necessary.  The information is then distributed through the cloud to the affected parties.

“A significant problem we have in the semiconductor industry is making the management of data of secondary importance, over the development of new technology” said CEO Thomas Grebinski, “when, in fact, it is the very source of our innovation.”

Grebinski has put his thumbprint on the semiconductor industry for a couple of decades.  He dealt with how ICs are physically composed by pioneering atomic layer deposition technology in the 1980s, he moved to developing a way to handle yottabytes of data as the author of the the OASIS integrated circuit layout format standard of SEMI.  Now he’s taking on how that data can be managed, distributed and protected efficiently and effectively.

He wants to look at the collective wisdom and understanding in databases around the world.  He believes that the answers to many of the difficulties in semiconductor design -- be it power, speed or latency -- exist somewhere in that massive amount of data.  The problem is that the human mind cannot comprehend what is before them, what he calls “Big Thought™”.

“Our biggest problem in semiconductor design is not creating new technology, but interpreting the data at hand.  That alone represents up to 50 percent of the NRE,” he claims.

Grebinski said changes in design often come from multiple sources, often in the form of “black boxes” to protect proprietary IP.  It is sent out to multiple engineering groups who have the responsibility of determining if the change affect their particular project.  That effort contains enough guesswork to insert significant risk in a given project.

Grebinski has been working with a few significant semiconductor companies to install the technology internal to each company to allow the engineers to find what they need in a timely manner and effectively document their engagement.

“This approach collapses the time spent by engineers deal with data -- the largest single component of NRE -- to virtually nothing by managing the data computationally, rather than manually,” Grebinski claimed.  “This reduces a significant amount of risk associated with semiconductor design and manufacturing and can bring the cost of developing new products below the $25 million threshold immediately.”

Grebinski sees this technology has uses in the development of IP at the highest level (ESL) can make the use of tool suites more effectively, and coordinate the efforts of design services between in-house and outsourced teams.

Reducing the cost of complex IC development to a profitable level has no one answer, but it seems the combined answer is closer than we realize.

covey_louLou Covey is founder, CEO and president of Footwasher Media. Lou has been a communications consultant leading electronics firms including NEC Electronics and Mitsubishi Electronics America, Inc. Cadence Design, Magma Design Automation and Synopsys.

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