Synopsys’ Formality Ultra Speeds the functional ECO process

Last Friday, Gal Hasson gave me a sneak peak at the functionality announced today in Synopsys’ new Formality Ultra product.  Formality Ultra is an add-on for Synopsys’ industry-leading formal verification tool, Formality.  It addresses challenges engineers face in what is becoming one of the most costly aspects of silicon design projects, functional engineering change orders (ECOs).  Through surveying their customers, Synopsys found that increasingly, customers identified functional ECOs as a source of project delay and unpredictability.  ECOs are often caused by bugs that elude detection until late in the design process.  Increasingly,  however, with today’s rapid market fluctuations, they are caused by very late changes to the specified and/or required functionality of the device itself.  When ECOs arrive, designers can address them in one of two manners.  They can make a functional change in the RTL and then propagate that change through the entire design process requiring functional verification, synthesis, and place and route to be redone, or they can short circuit the process by directly changing the netlist, and adding the corresponding change to the RTL.  Formality Ultra can cut the time required for ECOs in half by optimizing this second method in the following three ways

  1.  It helps the designer zoom into the portions of the netlist affected by an ECO.
  2. It can formally verify the correctness of an ECO change in minutes as opposed to hours.
  3. It generates scripts to pass the ECO on to Synopsys’ IC Compiler place and route tool.

Using Formality Ultra, a designer can quickly identify the portions of a netlist associated with a particular bit of RTL functionality.  Once the specific portion of the netlist has been identified, the designer can immediately make their netlist changes as well as the associated changes to RTL.

Upon completion of the changes, Formality Ultra can be used to formally verify that the netlist changes are equivalent to the associated RTL changes.  The tool identifies and verifies only the logic cones that are affected by the netlist change.  Formality Ultra’s advanced engine allows it to determine in what order to verify the cones so that they can all be verified concurrently without additional user input.  Because the advanced engines in Formality Ultra can do this in a number of minutes instead of hours, the designer can try several equivalent netlist changes to perform what-if analysis and select the edit that is best suited to the project.

Once the netlist changes have been made and formally verified, Formality Ultra automatically generates the scripts to hand the ECO off to the next step of the process, place and route.

Formality Ultra is compatible with version of 13.03 and all future versions of Formality and has been in use at partner customer sites since March of this year.  When asked about their experience with Formality Ultra, Synopsys customer Cavium, remarked that it had cut their ECO cycle time in half which had led to two key advantages.  First, their schedules had become more predictable.  Second, now that their ECO cycle time was down, they were able to roll features into devices that would have been otherwise delayed to future  revisions using their previous ECO flow.

If you’d like to learn more about how Formality Ultra can help with your ECO design challenges, contact your local Synopsys sales rep today.

A demo of Formality Ultra can be seen at:
http://www.synopsys.com/apps/formality-demo/formality-ultra.html

Hamilton Carter is the Chief Consultant at Pythagorean Productions. He has formerly worked as an engineer at Toshiba and Cadence Design Systems. Hamilton graduated from Ohio State University.

EECatalog Tech Videos

MAGAZINE

  • Download the latest issue of the Chip Design Magazine
    and subscribe to receive future issues and the email newsletter.

©2014 Extension Media. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS