Trio contributes to Accellera Systems tool interoperability
ARM, Cadence Design Systems and STMicroelectronics have collaborated to provide new interfaces to increase model and tool interoperability for ESL design at the transaction level. The contributions are intended to “significantly improve” the integration of SystemC models in virtual prototypes and provide standard interfaces to extend hardware/software integration and debug capabilities using appropriate tools.
Describing the interfaces as “crucial” to strengthening the ESL ecosystem, Philippe Magarshack, executive vice president, Design Enablement & Services, STMicroelectronics, said: “Eliminating the need for adapters will increase virtual prototype simulation performances, [and] enable . . . faster hardware-software integration”.
The first technical proposal addresses interoperability among SystemC TLM (Transaction Level Modeling) and proposes a standard interface to model interrupts and wires at the transaction Level. Models from different companies will be seamlessly integrated with standardized memory-mapped connections. The aim is for this to encourage the growth of a market for third-party TLM models.
The second proposal defines a standard interface between models and tools to support register introspection, enabling tools to seamlessly display and update register values. The interface works in different, user-defined register classes, supporting platforms integrating heterogeneous models from different model providers. This capability is described as a key enabler for the integration and debug of embedded software on pre-silicon virtual prototypes.
Finally, an approach is proposed to reconstruct system memory maps as seen from initiators, enabling ESL tools to support hardware/software debug on complex virtual platforms and improve productivity for hardware/software multi-core systems. (Memory maps depend on the interconnection of models, so each system initiator might have its own view.)
APIs and implementations, documentation and examples are available under an Apache 2.0 open-source license (http://forums.accellera.org/files/).
The three companies will work within the Accellera Systems Initiative to refine and standardize the proposals.
EC funding continues for IC services
Reassurance has been won for Europe’s ASIC industry with the European Commission pledging to continue to fund the Europractice IC services for another three years.
As a result of the funding, partners imec, the UK research Science and Technology Facilities Council (STFC), and the Fraunhofer Institute for Integrated Circuits IIS (Fraunhofer IIS) will continue to develop European ASIC-based products to market.
Carl Das, Director of the Europractice IC service at imec said: "The EU’s continued support of the Europractice IC services speaks to the value of our efforts to help get European ASIC-based products to market quickly and cost effectively.”
The FP7 (Seventh Framwork Programme) announcement means that the group can continue to provide universities and academic institutions in Europe and worldwide with MPW protoyping and packaging services. It offers European academics access to state-of-the-art design tools and, to industry worldwide, it also offers microelectronic and microsystem design services, small volume production, packaging and test operations with industry design, development, prototyping and manufacturing ASIC services on a cost-sharing basis. Today, about 500 universities, 150 research centers and more than 200 European companies have access to these services.
Europractice IC services offers dedicated training courses on design flows and methods in advanced technologies, and has negotiated low-cost opportunities with the most popular industry-standard CAD vendors and foundries.
There are plans for the service to expand over the next three years to supplement ASIC services to MEMS and photonics technology services.
The European initiative is represented by Imec, based in Leuven, Belgium, which conducts nanoelectronics research with partnerships in ICT, healthcare and energy; the STFC which manages and operates the Rutherford Appleton Laboratory, Daresbury Laboratory and the UK Astronomy Technology Centre; and the Fraunhofer IIS, in Erlangen, Germany which performs nanoelectronics, IT, telecoms, audio and multimedia, RF technology, satellite navigation, medical engineering and industrial automation R&D for industry and public authorities.
Working group takes software approach to tackle multi-core embedded design
A working group will define the architecture description standard to reduce the cost of software tool support for multi-core and many-core processors.
The Multicore Association has launched the Software-Hardware Interface for Multi-Many Core (SHIM) working group to provide a common interface to abstract the hardware properties important to multi-core tools.
The program is designed to improve tool support to development tool vendors who can find the development scheme is thwarted by having to find support for virtually unlimited processor configurations. By defining the architecture description standard for software design, as opposed to defining and describing electronic components for hardware, as the IEEE IP-XACT standard does, the SHIM working group hopes to facilitate quicker time to market and promote confidentiality between processor vendors and development tool partners.
Architectural features that SHIM will directly or indirectly describe are the processor cores, the inter-core communication channels (in support of message passing protocols, such as the Multicore Association’s MCAPI), the memory system (including hierarchy, topology, coherency, memory size, latency), the network-on-chip and routing protocol, and hardware virtualization. The standard will be flexible enough to allow vendor-specific, non-standard architectural information for customized tools. However, while the standard will be publicly available, the vendor-specific information can remain confidential between a processor vendor and its development tool partners.
The standard will apply to many types of tools, including performance estimation, system configuration, and hardware modeling ones. The aim is to provide performance information pertinent to software, such as performance analysis tools, auto-parallelizing compilers, and other parallelizing tools, as well as basic architectural information for system configuration used by operating systems, middleware, and other runtime libraries.
One stated goal is to align the standard with work already underway in the Multicore Association’s Tools Infrastructure Working Group (TIWG).
28nm low-power process targets mobile applications
The joint development of a 28nm process to reduce leakage and power consumption has been announced by United Microelectronics Corporation (UMC) and SuVolta. The scalable semiconductor company’s Deeply Depleted Channel (DDC) transistor technology is integrated into the foundry’s 28nm High-K Metal Gate, HPM (high-performance mobile) process. It is targeted at mobile application processors, where these factors are important design challenges, but can also find uses in DRAM, imaging and microcontrollers, says SuVolta.
The semiconductor company’s DDC technology is presented as an alternative to both FDSOI (Fully Depleted Silicon on Insulator) and FinFET. Doping techniques are used to create a ground plane under a transistor, which has the advantage that it is without the cost premium of SOI wafers.
The technology to reduce leakage power and improve SRAM low-voltage performance is expected to be used in one of two methods. The first is a DDC PowerShrink, where all the transistors used are based on the DDC technology. The second is the DDC DesignBoost method. Here only selected transistors are replaced with DDC transistors to reduce voltage or reduce the operating power. This version can be applied to existing design transistors databases.
Alternatively, memory capability can be boosted by replacing SRAM bitcell transistors, to improve performance and lower minimum operating voltage in memory products.
T.R. Yew, vice president of Advanced Technology Division at UMC, said: “By incorporating SuVolta’s advanced technology into our HKMG process, we intend to deliver a 28nm mobile computing process platform to complement our existing Poly-SiON and HKMG technologies.”
According to Bruce McWilliams, president and CEO, SuVolta, the two companies will continue to develop a process to ease porting of customers’ designs, and believes that the transistor technology “is advancing future generations of mobile devices by providing the industry with an alternative” process technology.
In a previous role, as editor of EPD, she created the e-Legacy Awards and also managed and chaired EPN’s 40th Anniversary Forum at electronica 2012.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Karen Popp at +1 415-305-5557
Santa Clara, CA January 27-30, 2015
San Francisco, CA February 22-26, 2015
San Jose, CA March 2-5, 2015
Grenoble, France March 9-13, 2015
Mesa, Arizona March 15-18, 2015
Santa Clara, CA May 6-7, 2015
Encore at the Wynn Las Vegas, NV May 19-22, 2015