Published on August 13th, 2013
While PCI Express® has become the dominant I/O interconnect in PCs from ultrabooks to enterprise servers, it has not yet made significant inroads to the mobile and wireless space due to these applications’ ultra-low power requirements. Great strides have been made in reducing PCI Express power with enhancements like half-swing drivers, Dynamic Power Allocation (DPA) controls, and new power-saving L1 sub-states. However, the power required by PCIe PHYs to drive PCIe’s high data rates across 16- to 20-inch server channels is well above what mobile devices can tolerate. For PCI Express to extend into the ultra-low power world of wireless devices, something drastic had to be done.
Back in 2012, Synopsys and other companies founded a new PCI-SIG Working Group whose aim was to reduce PCIe power and bring its protocol, programming models, and wide spectrum of designs to the mobile space. Ultimately the group decided to replace the “legacy” PCI Express PHY with the MIPI Alliance’s M-PHY to take advantage of its proven power efficiency, range of speeds, and acceptance by the mobile industry. In September 2012, PCI-SIG and MIPI Alliance announced their collaboration with the ultimate goal of allowing device designers to easily move existing PCI Express designs to the new specification with little or no change to their existing PCI Express software infrastructure. Work proceeded quickly and by early 2013 the two groups announced the first version of the M-PCIe Engineering Change Notification (ECN).
The M-PCIe ECN provides dramatic power savings over similar PCIe designs. Note that because M-PCIe is an ECN against the PCI Express 3.0 Base Specification, both documents are needed to completely specify an M-PCIe device. Figure 1 shows how implementing the M-PCIe ECN impacts a typical PCIe Root-Complex to Endpoint device path. A standard PCI Express path is represented on the left, and the new M-PCIe connections are shown on the right. The upper PCIe protocol layers – the Transaction Layer (TL) and Data Link Layer (DLL) – are unchanged in the M-PCIe devices. This ensures that the PCIe programming models are unchanged, and the application logic in each device can remain almost unchanged. The PCIe PHYs are replaced by M-PHYs, and the PHY interface changes from PIPE to RMMI. The Logical PHY Layer (LPL) has undergone a transformation and is unique new logic for M-PCIe implementations.
|Figure 1: In the M-PCIe architecture, the PCIe PHYs are replaced by M-PHYs, and the PHY interface changes from PIPE to RMMI|
PCIe and M-PCIe devices have different designs for their Link Training and Status State Machine (LTSSM). The M-PCIe ECN developers strove to maintain similarity between the two state machines, but the M-PCIe version of the LTSSM is ultimately a different design. While this is a significant change to every PCI Express device, the modification was necessary to control the M-PHY’s unique low-power states.
As shown in Figure 2, the PCI Express PHY is designed to drive across 16- to 20-inch channels with as many as two sockets and two connectors. By contrast, the M-PHY is designed for use in much smaller, portable devices with no connectors. For example, the mobile phone PCB shown in Figure 3 is less than five inches overall, with numerous chip-to-chip connections under an inch. Basic physics tells us that it will take much less power to drive a signal over a one-inch run than over a 20-inch run. Thus the M-PHY, designed to drive much shorter trace lengths, can consume less power than a PCIe PHY at the same signaling rate.
|Figure 2: The PCI Express PHY is designed to drive across 16- to 20-inch channels with as many as two sockets and two connectors.¹|
|Figure 3: The M-PHY is designed to drive much shorter trace lengths such as in mobile phone PCBs, so it can consume less power than a PCIe PHY at the same signaling rate.²|
|Figure 4: By architecting for M-PHY power transitions, designers can minimize power consumption of active devices.|
M-PHYs reduce power even further due to the relationship between their operating mode and individual burst transfers. In an M-PHY design, the PHY is only at its maximum power while actually transmitting. Upon completion of the burst transfer, the PHY drops to a much lower power “STALL” state and shortly thereafter into its lowest power “HIBERN8” state. Figure 4 shows these transitions and gives an idea of the order of magnitude power savings – STALL being perhaps half the power of the BURST mode, and HIBERN8 being less than half of STALL. By architecting for these rapid power state changes, M-PHY designers have minimized the amount of power consumed by active devices, thereby enabling long battery life.
To further reduce power consumption, M-PCIe systems can implement asymmetric links, which allow for different numbers of transmitters and receivers on a link. The PCI Express Base Specification defines a PCI Express lane as having one transmitter and one receiver per device, ensuring that there are always an equal number of upstream and downstream lanes. Wireless devices frequently operate primarily in one direction – with client devices downloading much more data than they upload, for instance. Recognizing these asymmetric bandwidth needs, M-PCIe permits devices to implement whatever combination of transmitters and receivers is needed. Consider the hypothetical device shown in Figure 5, which primarily receives data from PCI Express and moves it over another interface such as a broadband cellular link. Where PCI Express forces this device to have four transmitters and four receivers (shown on the left) to accommodate its need for four lanes worth of PCIe-to-cellular bandwidth, M-PCIe (shown on the right) permits the device to reduce the number of transmitters to the required amount and in this case, only two.
|Figure 5: M-PCIe systems can implement asymmetric links to further reduce power.|
While the M-PCIe specification allows devices to consume less power than they would with the PCIe PHY, PCI Express offers higher speeds than M-PCIe. M-PCIe uses three of the M-PHY “gears” for signaling rates. Each M-PHY gear can run at one of two different base frequency “rates” (known as Rate A and Rate B), but in very general terms one can consider M-PHY Gear M as being the same bandwidth as the corresponding Generation (M-1) of PCI Express signaling. So Gear 3 is roughly equivalent to PCI Express “Generation 2” (5.0 GT/s) signaling, Gear 2 roughly the same as PCIe “Generation 1” (2.5GT/s), and Gear 1 about half the bandwidth of PCIe “Generation 1.” Selecting an M-PHY for its power savings reduces the maximum trace lengths which can be used, and limits link speeds to less than what could be attained with PCIe’s “Generation 3” signaling – at least for today’s Gear 3. It’s important not to overlook the distinctions between rates A and B as they have been chosen precisely to avoid interference with different worldwide wireless standards. An M-PCIe device designed for worldwide use must support both the 1248 MHz frequency multiples of Rate A and the 1458 MHz frequency multiples of Rate B. Note that at Gear 3 speeds, the approximate 15 percent difference has widened such that Rate B is more than 800 MB/s faster than Rate A.
The M-PCIe ECN provides dramatic power savings for PCI Express architecture designs, which will enable their use in a much wider range of wireless and mobile devices than ever before. While the upper layers of the PCI Express protocol stack remain unchanged, it should be clear now that designers wishing to migrate designs from PCIe to M-PCIe will have some challenges. Prudent design choices in the M-PCIe interface controller, and careful consideration of these and other migration issues, can minimize SoC designers’ risk. Visit synopsys.com/m-pcie and follow the author at http://blogs.synopsys.com/expressyourself/ for more information.
Richard Solomon, Technical Marketing Manager, DesignWare PCI Express Controller IP, Synopsys
Richard Solomon has been involved in the development of PCI chips dating back to the NCR 53C810 and pre-1.0 versions of the PCI spec. Prior to joining Synopsys, Richard architected and led the development of the PCI Express and PCI-X interface cores used in LSI’s line of storage RAID controller chips. He has served on the PCI-SIG Board of Directors for over 10 years, and is currently vice president of the PCI-SIG. Richard holds a BSEE from Rice University and 25 US Patents, many of which relate to PCI technology.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
Chip Design now offers customized market research services.
For more information contact Jenna Johnson at 612.598.3446
Dusseldorf September 8-9, 2015
Boston, MA, United States of America 21-23 Sep 2015
Disneyland Hotel, Anaheim CA. October 6-8, 2015
santa Clara Convention Center, Santa Clara, CA November 10-12, 2015
anta Clara Convention Center, Santa Clara, CA Jan 19-21, 2016
DoubleTree, San Jose Feb 29-Mar 3, 2016
San Francisco, CA May 22-27, 2016