Published on August 26th, 2013

How Flash and DRAM Growth Trends are Reshaping the Memory Industry

Historically, one of the biggest growth drivers in the DRAM industry was the memory consumption in personal computing platforms. However, the definition of personal computing platforms has rapidly changed to be centered on mobile platforms (see Figure 1) as opposed to desktops and notebooks. In this new mobile world, the demand for DRAM memory has been affected because NAND Flash is being used in place of DRAM for the system memory requirements. The DRAM industry has reacted to these changes by finding growth in new, emerging areas like high-performance computing and high-performance networking.


Figure 1 - Mobile PC shipment growth

As the unending appetite for more mobility continues, the marketplace continues to be subjected to a pace of replacement never previously experienced. As quickly as notebooks became desktop replacements, now tablets are cannibalizing the notebook market.

One side effect of this cannibalization is that average DRAM consumption per device is on a downward trend. Traditionally, notebooks have had a minimum 4GB standard DRAM memory configuration whereas tablets are typically 1-2GB. Although the growth in tablet unit sales partly offsets this reduction, it's not enough to fill the void completely, as shown in Figure 2.

Figure 2 - DRAM module shipments

To ensure design success in such a volatile environment, comprehensive model support for current and new standards in both NAND Flash and DRAM are required to fully leverage performance and power improvements.

As the growth in the NAND Flash industry continues to accelerate (see Figure 3), the technology is facing some of its own growing pains. As mobile device users use more and more applications, and as those applications continue to grow in complexity and capability, the continued stress to provide larger and larger memory configurations with higher and higher performance has exaggerated the reliability and endurance challenges of these non-volatile memory technologies. This has had major impacts on both on-chip and off-chip error detection and correction.

When designing mobile memory subsystems, it is becoming more and more critical to be able to simulate not only the detection but also the response to these new reliability challenges. Accurate modeling of these effects ensures that performance is not sacrificed unexpectedly.

Figure 3 - Revenue growth by memory segment

As Internet penetration increases, the growth in high-speed communications and cloud computing are driving new demands on computer data center infrastructures for both public cloud (i.e. Amazon web services, Google web services, etc.) and private cloud services. These growing demands are resulting in new memory technologies targeted to meet these performance requirements (see Figure 4).

Figure 4 - DRAM technology trends in data processing applications

Virtualization of data center services is driving the expansion of these centers, which places increasing demands on cooling, back-up, and high-speed data transmission. To meet these demands, more memory types (like DDR4) are required with higher speed, higher density, and lower power consumption. Beyond DDR4, new technologies like High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), and Wide I/O II are being developed at an aggressive pace to provide next-generation solutions.

However, the data center demands are only half of the equation. On the client side, the growth in ultra-thin notebooks is growing at a rapid pace. With the focus on compact physical profiles, long battery life, and high performance, this trend is also requiring new memory solutions to meet these aggressive targets.

In the mobile memory space, the demands for higher performance, lower power DRAM solutions are resulting in the rapid introduction of new memory architectures (see Figure 5).

Figure 5 - DRAM technology trends in mobile

The mobile device market-including feature phones, smartphones, and tablets-is continuing to generate its own set of unique memory requirements. From the low cost of feature phones to the high-performance requirements of smartphones and tablets, new memory solutions are necessary to meet the storage and speed requirements.

Lastly, in consumer electronics, the demand for higher performance and unique solutions is driving the development and introduction of new memory technologies (see Figure 6).

Figure 6 - DRAM technology trends in digital consumer products

For everything from web TVs to Blu-ray recorders, set-top boxes, digital cameras, and game consoles, unique memory solutions are evolving to meet the performance/power/space demands of each of these markets.

In the portable consumer device market for digital cameras, handheld games, etc,. the drive continues for the succeeding memory technologies to follow the evolution from LPDDR to LPDDR2 to the emerging LPDDR3 technology.

For the non-portable consumer device market (where power and space are more readily available), increasing performance requirements are rapidly pushing past the ability of DDR2 and DDR3 to keep up, which has led to increasing anticipation of new DDR4 solutions.

In summary, the global impact of these changes is being felt in not only the rapidity of adoption of new technologies, but also in the extension of existing technologies and creation of new technologies in order to meet increasing performance, power, and mobility requirements.

To effectively compete in this new always-on, always-connected world, new product designs are being challenged to leverage every available ounce of performance and power from today's IC designs. With the rapid development and adoption of so many new technologies in both NAND Flash and DRAM, it is necessary to have a memory verification solution that not only supports today's standards, but also one that introduces support for new standards as rapidly as they are available.

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Scott Jacobson
Cadence Design Systems

Scott Jacobson is a product marketing manager supporting the Cadence VIP Catalog. Scott manages product marketing for the Memory Model Portfolio and Ethernet protocols.

Prior to this role, Scott has 20+ years experience in applications, sales and marketing roles in EDA. He began his career as a design engineer with Boeing Aerospace.

Scott holds a BSEE from Washington State University.

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