Typically, Structured ASICs have a much lower unit cost than FPGAs, and therefore converting an FPGA design to Structured ASIC can be a very attractive option when volumes exceed 5 or 10K pieces per annum. In addition to cost savings, there are other advantages in converting an FPGA to Structured ASIC. For example, Structured ASICs offer greater performance and use less power than an equivalent FPGA using the same process geometry.
With ASICs, the final production design can be tailored to fit the requirement. An example of this ability to tailor is that a wide selection of packages is usually available. If pin compatibility with the FPGA prototype is not required, the final production package can turn out to be considerably cheaper than the package the FPGA comes in.
Of course, there is an NRE charge for making any ASIC; however, for Structured ASICs, this charge is much less, and the turnaround time much shorter, than converting to a traditional Standard Cell ASIC. Structured ASICs have predefined products in which many physical design issues have already been considered. This allows the designer to get to market quicker and with less risk than previously possible.
When designing an FPGA prototype, it is important to plan ahead so that it can be easily converted to a structured ASIC or Standard Cell ASIC for production. Ideally some co- development work using both FPGA and ASIC libraries can be done at an early stage, but even without this, just a little bit of planning can make the conversion process painless.
Plan for Success: Design the Logic for a Smooth Transition
Whilst very tempting to use, proprietary intellectual property (IP) supplied by FPGA vendors is not always available for conversion to an ASIC. It's best to use IP that can be synthesized on both the prototype FPGA and the final ASIC. Where analog IP such as a phase-locked loop is used, ensure that your target ASIC vendor can match the frequency generation or deskew requirements that the design requires.
Of course, it is always best to use synchronous logic wherever possible. You might not be able to reproduce an FPGA asynchronous logic path in the structured ASIC.
FPGA I/O and FPGA RAM cannot be replicated in the ASIC. The designer needs to stay within the overall RAM capacity and number of RAM instances available in the Structured ASIC. Asynchronous RAM access and asymmetric read/write ports with different word widths may require extra wrappers and logic to be added. Furthermore, the FPGA allows memories to be initialized to a known state on power up. This is not usually possible in an ASIC, and will require a processor or external PROM with specific hardware added to perform the loading operation. Some FPGA I/O types may not have an equivalent cell on the ASIC.
Typically, test circuitry is not required in an FPGA, but untestable circuitry in an ASIC will lower the fault coverage for the device and may allow faulty parts to pass through the tester during production. The designer should therefore consider design-for-test requirements. Some ASIC vendors may do test insertion and automatic test program generation, but dedicated and multiplexed test pins may be required, and extra test circuitry may be needed.
Even though FPGAs don't require it, add reset and initialization logic. That way, test vectors used on the completed prototypes yield the same result as simulations.
Carefully Choose Your Design Tools
Most front-end synthesis tools can be used during the design, but it is likely that there will be different tools, or different versions of the same tool, used for FPGA synthesis and ASIC synthesis. Using a code checker and least-common-denominator coding style avoids mismatches in results.
The ASIC vendor requires timing information to perform synthesis, timing-driven layout, and post-layout static timing analysis. Providing good system clock information, an I/O system timing budget, along with any false/multicycle path information and the FPGA synthesis scripts, will speed ASIC layout.
There may be some temptation just to make a minor change on the FPGA and plug it in to see if it works without writing a new testbench, but when converting to the ASIC, you will not be able to check that this change works exactly as in the FPGA prototype. Use testbenches extensively to verify connectivity and timing differences when converting between the FPGA and ASIC.
Take Advantage of Packaging Choices
FPGA package selection is quite limited, but Structured ASICs have a wide range of packages, saving cost and board area. If pin compatibility with the FPGA prototype is required, discuss the pinout and package selection at an early stage with your ASIC vendor to ensure that your requirements can be met.
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