Published in December 2006 / January 2007 issue of Chip Design Magazine
Proper Planning Assures SoC Power IntegrityAt 90 nm and below, avoiding IR drop and electromigration problems becomes a crucial aspect of SoC design.
Of course, no single power-network architecture works for all designs. Design consultants in Synopsys' Professional Services group have employed the practices described in this article on many advanced designs. They provide a good starting point for assessing the best power-network implementation for an application. These practices include general guidelines for sizing and spacing top-level power rings, hard-IP perimeter power rings, standard cell power rails, and power and ground trunks. Because power-network synthesis can now automate some aspects of the planning/analysis task, this article offers suggestions for using this capability.
Before looking at specific power integrity practices, it's important to understand the basics of power planning. To ensure adequate power and ground connections for on-chip components, a power network generally includes the following basic elements (see Figure 1):
Power pads supply power to the chip.
Power rings carry power around the periphery of the die, a standard cell's core area, and individual hard macros. Typically, the rings are put in higherlevel routing layers to leave lower layers for signal routing. Note that rings also are generally useful around hierarchical blocks. In some cases, however, they consume more area than budgets allow. A good approach is to opt for a uniform global mesh and treat the hierarchical blocks as virtual blocks that have no physical power/ground rings around their peripheries. With this approach, however, the design is opened up to signal integrity issues across the physical hierarchy.
Figure 1: This conceptual drawing shows the structures used in a power/ground mesh.
Power rails (sometimes called row straps or standard cell preroutes), straps, and trunks cross the entire die or sections of the die. The horizontal wires are often referred to as rails while the vertical wires are referred to as straps or trunks. As with power rings, the widest trunks typically utilize the higher-level routing layers. Usually, the rails and straps are layed out as a uniformly spaced array. They are then modified to allow for hardmacro power rings, wiring keepout areas, and other restrictions. The power rails connect standard cell power pins together and then extend to the power rings. There, they connect with vias. After the straps and trunks are inserted, they should be tied together using vias and via stacks. Using low-level routing (typically METAL 1), rails are created only within standard cell placement areas that aren't already blocked by hard macro placements or wiring keepouts.
The resistance of the metal in this power-distribution network causes steady-state IR drop. By reducing the voltage difference between local power and ground, steady-state IR drop reduces both the speed and noise immunity of the local cells and macros. Furthermore, dynamic IR drop occurs when the simultaneous switching of on-chip components causes a dip or spike in the power/ground grid. The current pulled by simultaneously rising edges leads to a dip in the power grid. A similar phenomenon on falling edges leads to a voltage spike on the ground grid. Sometimes referred to as power bounce and ground bounce, respectively, these phenomena reduce logic gate noise margins. The resulting functional failures or timing errors are extremely difficult to anticipate with traditional signal integrity and timing analysis.
Electromigration occurs when large current densities cause a flow of metal atoms from the negative- to the positive-biased end of a length of interconnect. This flow can result in catastrophic failures by creating voids (opens in the metal line) or extrusions (shorts with neighboring metal lines). Electromigration has become a bigger problem as interconnect dimensions shrink, causing current densities to rise.
To avoid electromigration problems in power meshes, one must meet the maximum current density limits for the process as documented in foundry layout guidelines. When calculating the metal width required, bear in mind that straps wider than the process slotting size will be slotted at some point in the design process. As a result, their conductivity will be reduced.
Good power planning helps to prevent all of these power integrity problems. Developing the power network early helps to avoid many problems in the rest of the design flow. Plus, early, accurate analysis is essential. Some wires in the mesh carry more current than others. As a result, the current on every wire, junction, and via needs to be calculated.
Throughout the design process, it's important to calculate the power dissipation at the block level in order to determine if the design is meeting the specified power budget. Such calculations also help to estimate the size of the power grid. Early in the design process, manual calculations or spreadsheets can be used to estimate power. As the register transfer level (RTL) matures, design tools can be used to refine power estimates (+/- 30% is a reasonable target). As the RTL migrates to gates and transistors, the power estimates can be further improved. For final power signoff of the floorplan, use the actual netlist, the net switching activity corresponding to typical operating scenarios, and annotated parasitics.
(Please see the previous EDN article on power estimation/ analysis - which one is this?)
BUILDING THE POWER/GROUND NETWORK
With recent enhancements to floorplanning tools, the power grid can be synthesized based on chip power and voltage-drop requirements. Previous tool versions inserted power and ground rings. Their width and spacing had to be specified. When using those tool versions, a good rule of thumb is to assume that each side of the ring must carry 25% of the design's current. To get this value, divide the overall power budget by 4 and convert to current using the core's primary voltage. The required width can then be determined based on the allowed current density for the metal layer(s) used for the rings. If possible, limit this width to avoid the need for metal slotting.
It's a good idea to create power and ground rings around any hard macro. This practice enables orientation independence. It also eliminates the need for the chip's power structure to conform to the macro's power structure. Fortunately, most library vendors now produce hard macros with internal power and ground rings. In doing so, they improve the quality of the IP and simplify top-level power-grid planning. For any hard macros that don't include rings, use the quarter-current rule of thumb to determine the width of the rings.
Once the power rings are established, power and ground should be routed to the standard cell rows. Abutment of the cells accomplishes some connections. Use the floorplanner to add rails aligned with the power rails inside the standard cells. Use the lowest horizontal metal layer for these additional rails. To get a complete grid, some technologies and/or floorplans make it necessary to insert filler cells temporarily. After inserting the rails, remember to remove the filler cells.
The floorplanner makes the rail spacing consistent with the standard cell height. But rail width must be specified--most often using network synthesis tools that are aware of the process geometries. With the usual mirrored placement rows and their alternating power and ground rails, the width of the additional rails is larger than the width of the straps within the cells. Typically, the rail width and spacing increase at each successively higher metal layer. Wider rails can be used in the lowest metal layers. Yet they often result in the standard cell rows being spaced further apart. They therefore reduce the placement area and signal routability.
The straps and trunks that distribute power across the chip offer more flexibility than rings and rails. In addition, they represent the most important means to address specific IR drop issues. Based on design requirements, one must determine the appropriate spacing, width, and layer of these straps and trunks. To improve overall routability, it's usually better to use many thin routes (rather than fewer wide routes)--especially in the lowest metal layers.
BEST PRACTICES IN POWER PLANING
The following suggestions may prove useful for achieving good results in power planning:
1. Develop physical heuristics for the power/ground mesh.
All of the power and ground pads that supply the digital core should use a combination of METAL2 and METAL3 at a minimum for their pins. If other design constraints permit, METAL4 can be added. In general, it's best to have a uniform distribution of power and ground pads. Usually, specific suggestions and rules can be obtained from a foundry's layout guidelines documentation. When low-power cells are around the periphery of the die, however, putting power and ground pads near the die corners may provide almost no benefit.
Use multiple metal layers to connect the power and ground pads to the core ring. Assuming the standard cell rails use METAL1, use a combination of METAL2, METAL3, and additional higher-layer metal straps to improve the current capacity from the pad pins to the core ring. Depending on the number of metal layers in the process and the limit on stacked vias, it may be necessary to offset the METAL4 straps from the METAL2 straps in order to avoid long via stacks or "walls." Similar measures also may be required of the general power/ground mesh.
After accomplishing the standard cell power and ground straps, begin building the power/ground mesh two layers above the highest standard cell pin layer. This approach helps to minimize IR drop and provide for the best routability. If some cells present pins on METAL2, begin the power/ground mesh on METAL4.
When designing the power/ground mesh METAL4 layer, it's generally advisable to use spacing roughly 10X the size of the average standard cell width for the design library. Normally, the straps on lower layers supply a small local area. As a result, they don't need to be very wide. If the strap spacing on these lowest layers is minimized, the series resistance to any given standard cell also will be minimized.
Thinner wires that align well with the routing grid also improve signal routability. For a 0.13-`m process, for example, a spacing of 50 to 100 `m and a width of about 0.5 `m have worked well. Going up toward the top metal layer, the strap spacing can be gradually increased. The wires also can be widened. In subdesigns (soft macros), the "wrong way" power/ground mesh straps should be avoided (i.e., straps that don't use the preferred routing direction for that level).
2. Understand metal resistance characteristics for the target process.
Check vendor-supplied technology files to determine the resistance of each layer used in the power grid. Typically, the resistances for the top-most metal layers differ from the resistances of the lower-level metals due to the latter's greater thickness. Because of this difference, the voltage on the mesh may drop faster in one direction than the other. The result will be a non-uniform or "squashed" voltage gradient. This effect is especially noticeable in implementations that use an odd number of metal layers.
Non-uniform voltage gradient isn't necessarily a problem. Consider, however, the potential for problems when designing the power/ground mesh. To minimize this issue, remember that identical metal densities for all of the layers used in the power/ground mesh don't always imply a uniform IR drop and electromigration result.
Manually inserting power trunks and straps usually involves some degree of trial and error. Power-network-analysis (PNA) tools have gone mainstream in terms of usability and accuracy. But the designer still has to create the straps, run the analysis, and iterate as necessary until adequate results are achieved. Manual re-work can take as much time as first-pass implementation.
By providing automated power-network synthesis (PNS), tools like JupiterXT relieve some difficulties of the manual process. To use the tool, one simply fills out a form specifying the necessary structure. Variables are included, such as the maximum allowable voltage drop, ring widths and layers, and number of trunks. The tool begins by performing an analysis and synthesis of the power grid. It then performs PNA under the hood and displays the results. If the designer finds the results acceptable, he or she can commit them to the design. Otherwise, the synthesis can be rerun with refined constraints.
With the many degrees of freedom in creating such constraints, synthesizing power grids can seem like more of an art than a science. Given the differing requirements of each design and vendor, the engineer typically needs to explore possibilities until the analysis results look good. Fortunately, the iteration time is short. As a result, a lot of choices can be generated quickly.
As an alternative to full PNS, one can manually create a basic power grid. PNA can then be used to find regions that require refinement in order to reduce IR drop. PNS can be run on these specific regions. In addition, PNS can be used to size an existing power network to meet IR drop constraints. To accommodate new power requirements, the tool can resize mesh trunks automatically. Help also can be gained from power pad synthesis, which determines the number of power pads needed to meet voltage drop requirements and where they should be placed.
The way that power-network analysis (PNA) is performed depends on the tool that is used. In general, however, it's always a good idea to run PNA as early as possible. A tool like JupiterXT, for example, allows the engineer to run PNA with coarse placement and a partial power network. To run an analysis, one needs only a top-level power mesh without vias. The tool automatically creates virtual straps to model standard cell connections. It also can create virtual pads for what-if analysis.
Bear in mind that a more complete grid yields a more accurate analysis and better correlation as the design progresses through the flow. Be sure to include all rails, straps, rings, trunks, and via structures in the analysis before the final PNA during floorplanning. Because the power consumed by a cell depends on the load it drives, be sure the design is global-routed in the floorplanner to achieve best PNA results. Accordingly, floorplanner placement and global-route correlation to the detailed-route tool then become important.
Figure 2: For fine-grain power meshes, using a feature like "Optimize Track Usage" can save valuable routing tracks that would otherwise be wasted by power/ground routings.
PNS/PNA BEST PRACTICES
In parallel with the power-planning suggestions mentioned earlier, the following principles can help in achieving good PNS/ PNA results:
Focus on the top two metal layers for primary power and ground distribution and use a multi-layer mesh.
Make the lowest power/ground layer perpendicular to the standard cell power rails and at least two layers above the highest standard cell pin layer. This practice eliminates cell-placement and pin-accessibility issues for cells under the power mesh. It also improves the design's overall routability.
Be sure to define the following inputs:
Power-supply voltage value
Power-consumption value for the design core
Target IR drop
Turn on "Optimize Track Usage" in JupiterXT. Figure 2 shows how this option can conserve routing tracks next to power/ground routes.
To further increase/preserve routing resources for signal layers, align even the metal layers within the power structure and use stacked vias (see Figure 3). Do the same for odd metal layers.
Figure 3: For multi-layer power-network synthesis (PNS), aligning METAL4 and METAL6 increases route resources. The METAL6, METAL5, and METAL4 power grid is generated using multiple layer constraints.
The methods described in this article were developed by Synopsys Professional Services through multiple 90-nm implementation projects. They should offer starting points for assuring power integrity. Such methods are vital to ensure the performance of today's SoCs--especially for technology nodes of 90 nm and beyond.