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Taken For Granted

bloggerDATE 2010 Preview

The Design Automation and Test in Europe 2010 conference will be held in Dresden Germany from March 8 to 12. DATE...

Wizards of Microwave

bloggerUsing EM to Design DGS Structures

A Defective Ground Structure (DGS) is an intentionally designed defect on a ground plan, which creates additional effective...

JB's Circuit

bloggerGoing Beyond and Returning to Reusability

Design for the Consumer Era is seen as the next iteration of the infamous Design-for-X paradigm shift by keynote presenter at...

EDA Thoughts

bloggerCarbon Footprint is Good For ICs

IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs. | Photo...

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iDesign

iDesign - Providing the advanced IC Design market access to high-value information and essential tools. (Learn more)
Look for the gold star icon , featured on www.chipdesignmag.com, to discover content available exclusively to iDesign subscribers. All subscribers to Chip Design Magazine are automatically enrolled in an 8 week free trial. Click Here to ensure you are enrolled in a free trial.

Metric-Driven Verification: The Key to Achieving a... by Dylan Dobbyn, Verification Manager for Teradyne
(iDesign Subscribers )
Metric-driven verification makes the verification of complex designs far more manageable, enabling a closed-loop process...
C'mon Rock 'n' Chip Fans, Join the Chip... by Sanjiv Kaul, Executive Chairman of Oasys Design Systems
(iDesign Subscribers )
Yeah, this is a revolution – right here, right now. Buck up and get your wings. Rock your shop. Change your...
Static Timing Analysis at 28 nm: More and Bigger... by Robert (Bob) P. Smith, Vice President of Product Marketing within the Design Implementation Business Unit, Magma Design Automation
(iDesign Subscribers )
It’s clear that at 28 nm the traditional STA approach of increasing the amount of analysis, number of software licenses...

More iDesign Articles...

Featured Videos

  • Value Shifts In The Semiconductor Supply Chain

    System-Level Design discusses where the money has shifted in the semiconductor supply chain with Synopsys, eSilicon, TSMC and Avago.

  • Challenges At 32nm And Beyond

    Wally Rhines, chairman and CEO of Mentor Graphics, talks about what's changing in design, the effect of low power, and who's going to be doing the most advanced designs.

  • Tesla: The Ultimate Low-Power Design

    When your battery pack alone costs $30,000 and you get 200 miles per charge, you've got to be looking for ways to save power. The Tesla roadster is crammed with parts from many Silicon Valley companies, all designed to draw as little power as possible. But there's still much more work to be done.

  • Artificial Intelligence: This Time It's For Real

    AI used to be the stuff of science fiction, but cheap processing power and storage has made it a reality. To find out what's being developed, System-Level Design (www.chipdesignmag.com/sld) tracked down Rachel Goshorn, assistant professor of System Engineering at the Graduate School of Engineering and Applied Science in the Naval Postgraduate School in Monterey, Calif. Check out what she has to say.

  • New Memory Technology Ahead

    Christophe Chevallier, vice president of engineering at Unity Semiconductor, sat down with System-Level Design Contributing Editor Pallab Chatterjee to talk about multilayer technology that could boost chips to more than a terabyte using standard CMOS processes.

  • Saving Power By The Milliwatt

    Power budgets may look small, but the amount of power that can be saved with different design approaches will surprise you.

  • What Goes Wrong

    The best way to figure out where the problems are with products is to check with customer service. They hear everything. So System-Level Design sat down with Tom Flodeen, VP of customer service at Mentor Graphics to see where customers are asking questions. Yeah, we know there's a little marketing in this, but it's worth wading through to listen to what's going on behind the scenes.

more videos…

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