Si2 Announces “OPS Comes to Life” Session for Si2 Roundup@DAC
OCP-IP Releases New Compliance Document into Member Review
OCP-IP Releases OCP 3.1 Specification into Member Review
Accellera Systems Initiative Hosts User Events at the 2012 Design Automation Conference
OCP-IP Delivers Enhanced Transaction Generator Package
GSA Reports an Increase in April Semiconductor Funding Activity
Si2 Announces New Session for “Si2 Roundup@DAC”
GLOBALFOUNDRIES Fab 8 Adds Tools to Enable 3D Chip Stacking at 20nm and Beyond
Si2 Announces “Si2 Roundup@DAC: Standards in Action”
GSA Reports A Decrease in March Semiconductor Funding Activity
GLOBALFOUNDRIES Dresden Fab Ships 250,000th 32nm HKMG Wafer
IBM and GLOBALFOUNDRIES Begin First Production At New York's Latest Semiconductor Fab
If you are attending DAC this year, or still thinking about it, then read on -- you will not want to miss out on all the...
On April 23, 2012 Intel introduced their new Ivy Bridge Core processors for the desktop, All In One (AIO) and traditional...
The romance between hardware and software sours, then sweetens after a "three-some". But no divorce is planned. - Review by...
The path forward may be more focused on matching goals at the architectural stage, and then being able to swap information as a design progresses. Software is the next big target in
iDesign - Providing the advanced IC Design market access to high-value information and essential tools.
How to Pick the Best Verification IP for Your... by Tom Hackett Sr. Product Marketing Manager, Cadence
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Fast and New Method for Cycle Slip Analysis in... by Akmarul Ariffin Salleh, Agilent Technologies
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The Next Big Challenge by By Ed Sperling, Contributing Editor
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Embedded software test tools are a growing market by Lou Covey, editorial director
)The explosive growth of portable and wireless technology is a driver for similar growth in embedded software development....
The problem comes in when you are not a software-centric company. The 2012 UBM Embedded Market Survey showed that, for the first time, QA engineers are becoming a significant portion of embedded software teams, and while the quality of debugging tools is still the top area for improvement, engineers seem to be getting more confident with what is available. However...
Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.
eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.
Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening.
Interview with Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES. DAC 2011. Demonstrating 32/28nm design, 20nm technology. Design Enablement, ChipEstimate.com IP Talks 2011
This DAC Pavilion Panel explores technical and business issues related to SoC verification by panelists from ARM, AMD and Qualcomm.
Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?
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For more information contact Karen Popp at +1 415-305-5557
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