• A Meaningful Present for the New Year
• A Quick History of Clock Domain Crossing (CDC) Verification
• Hardware-Assisted Verification and the Animal Kingdom
• Advanced Sign-off…It’s Trending!
• Learn about Advanced Sign-off Verification at DAC 2011

• Microsoft Touts DFM for Systems and Chip Design
• DesignCon: Analog Scaling Requires New Design Techniques
• Will Patent Trolls Liquify the IP Market?
• Xilinx Expands Platform Strategy for 28nm FPGAs
• Next-generation Memory Vendors Seek New Markets

iDesign - Providing the advanced IC Design market access to high-value information and essential tools.

Microsoft Touts DFM for Systems and Chip Design by Mark LaPedus
(iDesign Subscribers )
Software giant also sees IC scaling challenges

Panel: Analog Scaling Requires New Design... by Mark LaPedus
(iDesign Subscribers )
Disconnect Seen for Mixed-signal Chip Design

Xilinx Expands Platform Strategy for 28nm FPGAs by Mark LaPedus
(iDesign Subscribers )
Products aimed to speed up development times

Startup Packet Plus Rolls Embedded Debugger by Mark LaPedus
(iDesign Subscribers )
Technology speeds up product development times

More iDesign Articles >>

• Strategy And Technology: One On One With Wally Rhines

  Mentor's Chairman and CEO sounds off about where the IC design challenges are, what needs to be done to fix them, and what new opportunities will unfold.

• One-On-One: Jack Harding

  eSilicon's CEO talks with System-Level Design about changes in design at advanced nodes, the power of 2.5D and 3D stacking, and how the semiconductor supply chain is changing.

• One-On-One: Naveed Sherwani

  Open-Silicon's CEO talks with System-Level Design about getting the business priorities of designing a complex SoC in line with the technology; why getting chips out the door on time is critical and why it's not happening.

• Walter Ng, GLOBALFOUNDRIES at DAC 2011 - IP Talks presenter

  Interview with Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES. DAC 2011. Demonstrating 32/28nm design, 20nm technology. Design Enablement, ChipEstimate.com IP Talks 2011

• Verification: What's in Your Wallet?

  This DAC Pavilion Panel explores technical and business issues related to SoC verification by panelists from ARM, AMD and Qualcomm.

• Ed Sperling on Low Power Pavilion Panel

  Ed Sperling, Chief Editor of Low Power Engineering, will host the Low Power panel at DAC 2011.

• Hogan's Heroes at DAC 2011

  Jim Hogan talks about the Hogan's Heroes panel - The Re-aggregation of Ecosystem Value.

more videos >>

Are you up-to-date on important SoC and IP design trends, analysis and market forecasts?

Chip Design now offers customized market research services.

For more information contact Karen Popp at +1 415-305-5557

• MEMS and Packaging Hold Keys to Radio Connectivity
  Building on Intel’s Rattner introduction to the future of mobile computing, IMEC’s Liebet Van der Perre recently spoke about the need for ultra-low-power, ultra-high-speed, versatile radios. Dr. Van der Perre is the director of the Green Radios Program at IMEC. What follows is a summary of her presentation.
• Globalfoundries Confronts Issues and Plans Ahead
  While the theme of collaboration was the same, the discussions at this year’s Globalfoundries GTC2011 event focused on supporting legacy nodes, acknowledging present challenges at 32nm and moving ahead to 28nm and 20nm with a strong ecosystem of partners.
• Sonics and Others Evolve On-Chip Interconnections
  Connecting a multitude of internal and third party IP requires ever advancing on-chip bus technology from big players like ARM, OCI-IP and INTEL as well as startups like Arteris and Sonics.
• EDA Inflections on Technology Innovations
  Each of the major semiconductor EDA companies approaches innovation is different ways, but all agree that creating new products and improving existing ones is essential to survival.

More Focus Reports >>

• EdXact: Bringing Innovation Into The Verification Flow

• InCyte

• Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros

• Platform Express

Click here for more >>

• Engineering – The Lost Profession
• ITC 2011 Special: Battle Brews Over Test
• What Debug and Medicine Have in Common
• The Economics of Innovation

More commentary >>

• Linking Early Mechatronic System Analysis to Physical Testing

• Best Practice Development Processes for Medical Device FPGAs

• Direct Power MOSFET Capacitance Measurement at 3000 V

• Common Pitfalls in PCI Express Design

• Increasing Revenue Through Continuously Optimized Data Center Management

• Designing For Low Power

More White Papers >>

• Micron CEO Steve Appleton Dies in Plane Crash
• Novellus Sees China, Wafer-Level Packaging, 3D NAND as Market Drivers
• Soitec Completes Acquisition of Altatech
• Editor's View: Tough Power Choices
• Semico Spin: 36% of Semiconductor Fabs at Risk from “Ring of Fire”

Sponsored by:

• The Next SoCs
• Derivative Designs Demand Discipline
• Software Takes Control
• Editor's Note: Redefining Design Starts
• ESL Edge: Power Matters

Sponsored by:

• Power Model Complexity Grows
• Material Effects: Trading Performance For Power
• Low Power Dominates CES
• Editor's Note: Margin Call
• Absolute Power: iPhone Antennagate Solved

Sponsored by:

• Chip Design Resource Catalog
• Chip Design Buyers' Guide
• Interoperability Guides
  • Cadence and Third-Party Solutions Guide
  • Mentor Graphics Vanguard Partner Interoperability Guide
  • OCP IP Member Guide
  • Synopsys - Focus on Interoperability
• IP Solutions Resource Catalog
• Valuable Resources
  • AdvancedTCA
  • DSP
  • FPGA and CPLD Resource Catalog
  • MIPS ® Embedded Resource Catalog
  • Multicore
  • PCI Express

Click here for more >>