TOP STORIES

Legacy vs New IP - Trends in IOT JPG and Drone Apps At REUSE, Meredith Lucky from CAST talked about the resurgence of legacy semi IP, parallelized JPG compressors for high def IOT and Drone system and more. read more

Grant Pierce Named BoD Chair of the ESD Alliance The Board of Directors of the ESD Alliance has named Grant Pierce CEO of Sonics as its Chair read more

Make Chips Do More and Last Longer with Embedded FPGA Data centers want programmable chips so they can upgrade the data center’s ability during the life of the center without touching the hardware read more

Tech Travelogue Feb 2017 - FIT, Reliability and Siemens-Mentor Acquistion Topics include the Florida Institute of Technology’s jet dragster, reliability and resilience in automotive systems and Siemens a... read more


Blogs

Gabe's EDA

Grant Pierce Named BoD Chair of the ESD Alliance
blogger

Gabe Moretti, Senior Editor The ESD Alliance (ESDA) has elected Grant Pierce (CEO of Sonics) as its Chairman of the...

Ed's Threads

Flagello to receive Zernike Award at SPIE Advanced Lithography
Donis Flagello, president, CEO, and COO of Nikon Research Corporation of America (NRCA), will be presented with the 2017...

Chipworks

Intel's 10nm Enigma
By Dick James I’ve been looking back at the talk given by Mark Bohr and Zane Ball (Building Winning Products with Int...

Pete's Posts

The New Driver for Semiconductor Tech
Over the past 40 years, the electronics industry has gone through three distinct stage or “waves” of evolution. Last yea...

JB's Circuit

Beginning the Discussion on the Internet-of-Space
blogger

A panel of experts from academia and industry assembled at the recent IEEE IMS event to answer critical questions are the...

MEMS Industry Group

Sentimental Feelings Looking Back and Forward to MEMS & Sensors Executive Congress
By Karen Lightman, Executive Director, MEMS & Sensors Industry Group Im feeling sentimental as I prepare with the...

IC Design

Context-Aware Latch-up Checking
blogger

By Matthew Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics Latch-up in CMOS circuits is a...

All Things Embedded

Does Secure Erase Actually Work?
Chris A. Ciufo, Editor, Embedded Systems Engineering In this Part 2 of 2, I examine the subject of using the flash ma...

NEWS, ANALYSIS & FEATURES

Featured Solutions

Mixel’s MIPI C-PHY/D-PHY Combo

Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as a MIPI Master or MIPI Slave supporting ... more

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Datasheet Directory

    EDA Tools

    Verification Functional

  • by AMIQ EDA

    Design and Verification Tools (DVT) is an integrated development environment (IDE) for the e language, SystemVerilog, Verilog, and VHDL. It helps design and verification engineers...

  • by AMIQ EDA

    Thorough audit of your test benches Verissimo SystemVerilog Testbench Linter is a static code analysis tool that allows engineers to perform a thorough audit of their testbenches....

  • Methods / EDA Tools

  • by ClioSoft Inc.

    ClioSoft ClioSoft’s SOS Design Collaboration Platform is built to handle the complex requirements of system-on-chip design flows. The SOS platform provides a sophisticated multi-site...

  • Design-for-Test (DFT)

  • by Source III, Inc.

    Source III provides the industry’s most comprehensive and cost-effective vector translation product (VTRAN®) which links simulation/ATPG vector data to ATE, a powerful vector...

  • by Source III, Inc.

    With nearly 25 years of field-proven success, VTRAN™ offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG vectors....

  • Verification

  • by Agnisys

    IDesignSpec™is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Agnisys

    IDesignSpec™ is an award winning Electronic Design Automation tool that allows an IP, SoC, or System Designer to create the register map specification once and automatically...

  • by Excellicon

    Organizations: EDAC, GSA, Si2 Constraints-Manager (ConMan), Constraints-Certifier (ConCert), Exceptions Toolbox and Clock Domain Crossing Review (ConDor) End to End timing...

  • by Real Intent

    Meridian CDC is the fastest, highest capacity and most precise clock domain crossing (CDC) solution in the market. It performs comprehensive structural and functional analysis...

  • by Sutherland HDL, Inc

    Founded in 1992, Sutherland HDL has trained thousands of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM. WORKSHOP HIGHLIGHTS Verilog and SystemVerilog...

  • Semiconductor Technologies

    IP - Core

  • by Calypto Design Systems

    Accelerate Time to Rtl, Reduce Verification Effort
    The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level.

  • by Calypto Design Systems

    With the explosion of consumer electronics, designing for low-power has become an important design constraint and a key differentiating factor. The RTL design phase provides the ideal opportunity to dramatically reduce power, since several micro-architectural transformations can be done at this stage, both via automated tools as well as manually by the RTL designers.

  • by Calypto Design Systems

    The emergence of consumer electronics is causing a fundamental shift in Register Transfer Level (RTL) design methodologies. The race for time to market has resulted in the adoption and growth of higher level design creation methodologies. In particular, High Level Synthesis (HLS) directly from software models to hardware has become very popular.

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance Mixel’s MIPI C-PHY/D-PHY Combo is a high-frequency low-power, low-cost, source-synchronous, physical layer. The PHY can be configured as...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance D-PHY RX+ is a CSI and DSI D-PHY Receiver optimized for small area and low power, while achieving full-speed production testing, in-system...

  • by Mixel, Inc.

    Organizations: GSA, MIPI Alliance The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI® Alliance Specification for M-PHY®....

  • by SmartDV Technologies India Private Limited

    Organizations: EDAC, GSA, EIC, OCP-IP, Si2, SPIRIT SmartDV offers wide range of Verification IP’s, Memory models and Design IP’s. Verification models include complete...

  • by True Circuits Inc.

    Organizations: GSA The TCI DDR 4/3 PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually,...

  • by True Circuits Inc.

    Organizations: GSA True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically...



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