Going, Going, Almost Gone
There has been a trend over the past several years in the electronics community. It has been driven by the dismal economy...
ISSCC 2010 – Low power designs back on track By Anand Iyer
Importance of low power has never been more pronounced as with this year’s ISSCC. Low power designs were highlighted in...
Freeman Dyson - Biotech vs Nanotech Continues
Thanks to all of the folks who responded to my original critique concerning Dr. Feeman Dyson’s December’09 lecture in...
SATA Connector Model in High Speed Digital Design
Due to the faster data transfer rate required in today’s consumer electronics market, interconnect design, such as Serial...
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Accelerating Media Processor Development using... by Avner Fish, Sigma Designs Inc.
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Billions of Cycles for Billions of Gates by Lauro Rizzatti, General Manager of EVE-USA
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Metric-Driven Verification: The Key to Achieving a... by Dylan Dobbyn, Verification Manager for Teradyne
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C'mon Rock 'n' Chip Fans, Join the Chip... by Sanjiv Kaul, Executive Chairman of Oasys Design Systems
)Intel Corporation legend, former CEO, and Chairman of the Board Craig Barrett discusses his personal career path from a Stanford Associate Professor, to Silicon Valley consultant, to a 35-year career inside one of the globe's most prominent players in technology. His talk concentrates on Moore's Law and the myriad factors in place to ensure its continued progeny.
System-Level Design discusses where the money has shifted in the semiconductor supply chain with Synopsys, eSilicon, TSMC and Avago.
Wally Rhines, chairman and CEO of Mentor Graphics, talks about what's changing in design, the effect of low power, and who's going to be doing the most advanced designs.
When your battery pack alone costs $30,000 and you get 200 miles per charge, you've got to be looking for ways to save power. The Tesla roadster is crammed with parts from many Silicon Valley companies, all designed to draw as little power as possible. But there's still much more work to be done.
AI used to be the stuff of science fiction, but cheap processing power and storage has made it a reality. To find out what's being developed, System-Level Design (www.chipdesignmag.com/sld) tracked down Rachel Goshorn, assistant professor of System Engineering at the Graduate School of Engineering and Applied Science in the Naval Postgraduate School in Monterey, Calif. Check out what she has to say.
Christophe Chevallier, vice president of engineering at Unity Semiconductor, sat down with System-Level Design Contributing Editor Pallab Chatterjee to talk about multilayer technology that could boost chips to more than a terabyte using standard CMOS processes.
Power budgets may look small, but the amount of power that can be saved with different design approaches will surprise you.
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