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Global Technology Conference 2010 will feature our GLOBALSOLUTIONS partners which provide a range of differentiated products/services from EDA, IP, design services, reticles, assembly and test.
We start off this issue with another take on how the Open Core Protocol (OCP) is influencing new IP design and development. OCP Application in Vector Graphics Hardware IP Solution by Eisaku Ohbuchi of DMP Inc. is one of the more colorful articles we’ve received, full of intriguing eye candy. Then we consult Ed Sperling on where IP is going, consider new memories in SoC design, and check for cracks in our 3D future.
To see our additional newsletters please visit: www.chipdesignmag.com/enewsletters/
EVE - HW/SW CO-VERIFICATION WORLDWIDE LEADER
For hardware verification engineers and embedded software developers, EVE’s ZeBu platforms are used to debug SOC hardware, accelerate embedded software development ahead of silicon availability, and ultimately shorten time to tapeout and improve design quality, while avoiding the drawbacks of traditional acceleration/emulation/FPGA prototyping systems.
By Eisaku Ohbuchi, DMP Inc.
Since the introduction of the iPhone in recent years, providing a superior user-interface with advanced graphics mechanism has become a big key to product differentiation. A highly-developed user interface in an embedded system will ensure a high quality user experience. SoC developers demand efficient and extensive graphics functions and so IP developers are confronted with difficult choices in providing graphics functions with a suitable ROI.
There are various ways to optimize the graphics functions for the user interface. For instance, a basic, primitive drawing of the line etc. is sped up by using DSP, drawing of 2D sprite is sped up by integrating a dedicated BitBLT module and, according to circumstances, more advanced graphics function can be achieved by introducing a 3D graphics core and so decrease the load on the CPU. However, there are pros and cons, and these are shown together in Table. 1.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=4321
Silver Sponsor: Mixel
Mixel is a leading provider of mixed-signal IP cores to the semiconductor and electronics industries. Mixel’s mixed-signal IP portfolio includes high-performance PHYs (D-PHY™ & M-PHYSM), SerDes, Transceivers, PLLs, and DLLs, which are used in mobile applications, such as MIPI, MDDI, networking, and storage.
By Ed Sperling
The rapid consolidation of the IP business is raising big questions about who will be left, whether new companies will join, and what it means for chipmakers looking to buy IP.
In a period of one month Synopsys bought Virage Logic, which had just finished a buying spree of its own with the acquisitions of ARC and the IP business of NXP, and Cadence bought Denali. So what exactly does this mean for chipmakers? There are fundamental questions that need to be answered to fully understand this market.
http://chipdesignmag.com/sld/blog/2010/06/24/the-future-of-ip/
Virage Logic Corporation broadened its System-on-Chip (SoC) infrastructure IP portfolio with a new Integra product line. Based on the proven technology that the company acquired last year from NXP, IP includes advanced Multi-layer and Control networks, embedded Quality of Service (QoS) functionality as well as memory controllers for embedded SRAMs/ROMs. The Integra Multi-Layer and Control Networks connect with Virage Logic’s ARC processor family via industry standard AMBA interfaces and provide an easy hook-up to the recently introduced portfolio of Processor Peripherals. The QoS Engine also easily interfaces to the company’s Intelli DDR controllers, while the Integra Memory Controllers are optimized for use with Virage Logic’s SiWare Memory embedded SRAM/ROM memories.
Virage Logic >> www.viragelogic.com
MoSys, Inc. and Northwest Logic are offering integrated PCI Express 2.0 and DDR3 solutions. The PCIe 2.0 solution combines MoSys’ PHY for PCI Express 2.0 and Northwest Logic’s full-featured Expresso 2.0 Core, DMA Back-End Core, DMA Driver and Expresso GUI to provide a complete, pre-packaged PCI Express 2.0 solution. The DDR3 solution combines MoSys’ DDR3 PHY and Northwest Logic’s high-performance DDR3 SDRAM Controller Core and add-on cores (AXI/AHB, Multi-Port, Reorder, etc.) These solutions are available separately or as a single, fully integrated solution.
MoSys, Inc. >> www.mosys.com
Northwest Logic >> www.nwlogic.com
STMicroelectronics introduced the first embedded microprocessor that couples two ARM Cortex-A9 cores with a DDR3 (Third-generation double-data rate) memory interface. Manufactured in ST's low-power 55nm HCMOS (high-speed CMOS) process technology, the SPEAr1310 delivers high computing power and customizability for multiple embedded applications together with the high level of cost competitiveness offered by system-on-chip devices. The dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst-case conditions) for 3000 DMIPS equivalent.
STMicroelectronics >> www.st.com
Taiwan Semiconductor Manufacturing Company, Ltd. announced that its 0.25-micron One-Time-Programmable (OTP) IP now meets Automotive Electronics Council (AEC) standard AEC-Q100 specification. The IP is fully compatible with TSMC Bipolar-CMOS- DMOS (BCD), mixed signal/analog and standard CMOS logic processes and does not require additional processing steps. TSMC's 0.25-micron OTP IP passes AEC-Q100 grade 1 product qualification specifications, features fully tested at multi-probe electrical testability and supports the automotive industry's stringent 10-year data retention requirement in 125 degrees Celsius operating temperatures. It is designed to operate at single 5 volt supply voltage for read operations after programming at 7.5 volt.
TSMC >> http://www.tsmc.com/
Synopsys, Inc. has added DesignWare® 96 dB Hi-Fi Audio IP in the 40-nanometer (nm) and 55-nm process technologies to its portfolio of high-quality audio IP solutions. The company is the first IP provider to offer audio codecs, digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) in these advanced processes. The IP portfolio offers performance levels from 80 dB to 103 dB and is available in more than 20 different process nodes, from 180-nm to 60-nm, and now down to 40-nm. The IP is targeted for consumer electronic applications requiring Hi-Fi playback and record capabilities with very low power consumption and small silicon area, such as portable media players, mobile phones, smart phones, CD/DVD/Blu-ray players/recorders and digital cameras.
Synopsys, Inc. >> http://www.synopsys.com/
Tensilica, Inc. has added the Free Lossless Audio Codec (FLAC) decoder to its ever-growing library of software for its HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. Because it is not a proprietary format, is not encumbered by patents, and has an open-source reference implementation, FLAC has become increasingly popular.
Tensilica, Inc. >> www.tensilica.com
ARM and Microsoft Corp. today announced that they have signed a new licensing agreement for the ARM architecture. The agreement extends the collaborative relationship between the two companies. Since 1997 Microsoft and ARM have worked together on software and devices across the embedded, consumer and mobile spaces, enabling many companies to deliver user experiences on a broad portfolio of ARM-based products. Details of the agreement are confidential.
ARM >> http://www.arm.com/
Microsoft at the ARM Connected Community >> http://www.arm.com/community/partners/display_company/rw/company/microsoft
Intellectual Property takes many forms, even glue. In this piece, David Lammers recalls Pol Marchal putting a stacked 3D prototype on his desk at imec in Leuven, Belgium, last year. A visitor picked it up, examined it, and said “I don’t think this chip will work.” Marchal, principal scientist at imec’s 3D system integration program, took up the challenge and put the stacked die under a microscope. Pol found that mechanical stress had relaxed over time and the top die had delaminated. In his article David cracks open the how and why.
http://chipdesignmag.com/sld/blog/2010/06/24/stressing-over-3d/
Asia Symposium on Quality Electronic Design
Gurney Hotel, Penang, Malaysia
August 3-4, 2010
http://www.asqed.com/
Flash Memory Summit
Hyatt Regency, Santa Clara, CA USA
August 17-19, 2010
http://www.flashmemorysummit.com/
ESC Boston 2010
Hynes Convention Center, Boston, MA USA
September 20-23, 2010
http://esc-boston.techinsightsevents.com/
PCB West 2010
Santa Clara Convention Center, Santa Clara, CA USA
September 28 - 30, 2010
http://pcbwest.com/
SAME 2010 (Sophia Antipolis Forum on MicroElectronics)
Sophia Anipolis, France
October 6-7, 2010
http://www.same-conference.org/
Black Hat Abu Dhabi
Emirates Palace, Abu Dhabi UAE
November 8-11, 2010
http://www.blackhat.com/html/bh-ad-10/bh-ad-10-home.html
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Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
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