• Evolving the Coverage-driven Verification Flow

• Power Consumption at 40 and 45 nm

• Accurately Analyzing Power in a Simulink Software Model-Based Design Flow

• Capabilities to Maximize Productivity for FPGA Debug and Verification

• Synopsys White Paper: Understanding the real cost of prototyping hardware

• The PSP Model in RF CMOS Design

More White Papers...

Where will the device design growth be in ten years?

	Multicore
	Programmable
	Wireless
	Low-Power
	IP
	New Technology

View Results

• Experts At The Table: Where The Money Is
• Remaking The Design Landscape
• Accessibility Trumps Accuracy In Today’s Hardware Models
• Editor's Note: Apple’s Re-aggregation Anomaly
• ESL Edge: Carpentry Lessons Applied To ESL

Sponsored by:

• Experts At The Table: The Reliability Factor
• Verifying Low-Power Designs
• Low-Power Architectures Go Mainstream
• Editor’s Note: The Prius Wake Up Call
• Absolute Power: Fun Facts for the New Year

Sponsored by:

Value Shifts In The Semiconductor Supply Chain

more videos…

Chip Designer

Chip Designer Plus

PLD Designer

IP Designer & Integrator

SUBSCRIBE NOW

Find detailed information about thousands of commerically available IP blocks from more than 230 suppliers

• Chip Design Resource Catalog
• Chip Design Buyers' Guide
• Interoperability Guides
  • Cadence and Third-Party Solutions Guide
  • Mentor Graphics Questa Vanguard Program
  • OCP IP Member Guide
  • Synopsys Interoperability Guide
• IP Solutions Resource Catalog
• Valuable Resources
  • AdvancedTCA
  • DSP
  • FPGA and CPLD Resource Catalog
  • MIPS ® Embedded Resource Catalog
  • Multicore
  • PCI Express
• Visit Dot.Org
  • POWER Architecture ISA 2.06’s Stride N Prefetch Engines Boost Application Performance
  • 60-GHz Communication: A Total Makeover
  • Accellera Technical Sub-Committee Enables VIP Interoperability and Reuse

Click here for more...

• Android Will Revolutionize User Experience in the Digital Living Room
• Dr. Freeman Dyson Compares Biotech to Nanotech
• People in the News
• Key Findings Show Changes in ASIC/ASSP Prototyping

More commentary...